This add support for kernel 4.9 to the ar71xx target.
It was compile tested with the generic, NAND and mikrotik subtarget.
Multiple members of the community tested it on their boards and did not
report any major problem so far.
Especially the NAND part received some changes to adapt to the new
kernel APIs. The serial driver hack used for the Arduino Yun was not
ported because the kernel changed there a lot.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add upstream send AR724x PCIe patches to get the PCIe controller out of
reset during driver init.
The AVM Fritz 300E bootloader doesn't take care of releasing the
different PCIe controller related resets which causes an endless hang
as soon as either the PCIE Reset register (0x180f0018) or the PCI
Application Control register (0x180f0000) is read from.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Refresh patches. A number of patches have landed upstream & hence are no
longer required locally:
062-[1-6]-MIPS-* series
042-0004-mtd-bcm47xxpart-fix-parsing-first-block
Reintroduced lantiq/patches-4.4/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup
as it was incorrectly included upstream thus dropped from LEDE.
As it has now been reverted upstream it needs to be included again for
LEDE.
Run tested ar71xx Archer C7 v2 and lantiq.
Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
[update from 4.4.68 to 4.4.69]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Bump & refresh patches for all 4.4 targets.
Compile & run tested: ar71xx Archer C7 v2
Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit
only specified the lower bits. The upper bits also have to be unset when the
lower bits should only be set.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45522
Qihoo 360 C301 is a dual band wireless router supports 802.11n and 802.11ac.
Its chipset is AR9344 + AR9882 with two 16MB flashes.
This patch adds its initial support.
v2:
* use mtd_get_mac_ascii to fetch MAC address for ath10k.
* use ath79_register_pci to initialize AR9882.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
SVN-Revision: 42552
The built-in wireless MAC of the AR934x SoC can handle
external LNAs and the control signal of the LNAs can be
routed to any GPIO line. Add a helper function which
can be used to configure the GPIO lines.
The helper function will be used for AR934x boards
which are using externel LNAs to improve sensitivity.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 39215
The F1E Phy (AR8035?) requires additional bits to be
set in order to provide a fast and reliable connection
over gigabit links.
When enabled, the link doesn't suffer anymore from a small
package loss under load and the performance is improved
quite a bit as well. (203 mbit/s vs 112 mbit/s, iperf tcp).
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Patchwork: http://patchwork.openwrt.org/patch/4460/
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 38948
John Crispin