Remove various hacks for fast read, un-break device tree support Signed-off-by: Felix Fietkau <nbd@nbd.name>master
Felix Fietkau
8 years ago
parent
52c7375c13
commit
fa04682f21
@ -1,83 +0,0 @@ |
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--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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@@ -16,4 +16,8 @@ struct ath79_spi_platform_data {
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unsigned num_chipselect;
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};
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+struct ath79_spi_controller_data {
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+ unsigned gpio;
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+};
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+
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#endif /* _ATH79_SPI_PLATFORM_H */
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -79,8 +79,10 @@ static void ath79_spi_chipselect(struct
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}
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if (spi->chip_select) {
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+ struct ath79_spi_controller_data *cdata = spi->controller_data;
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+
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/* SPI is normally active-low */
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- gpio_set_value(spi->cs_gpio, cs_high);
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+ gpio_set_value(cdata->gpio, cs_high);
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} else {
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if (cs_high)
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sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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@@ -116,9 +118,10 @@ static void ath79_spi_disable(struct ath
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static int ath79_spi_setup_cs(struct spi_device *spi)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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+ struct ath79_spi_controller_data *cdata = spi->controller_data;
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int status;
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- if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
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+ if (spi->chip_select && (!cdata || !gpio_is_valid(cdata->gpio)))
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return -EINVAL;
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status = 0;
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@@ -131,7 +134,7 @@ static int ath79_spi_setup_cs(struct spi
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else
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flags |= GPIOF_INIT_HIGH;
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- status = gpio_request_one(spi->cs_gpio, flags,
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+ status = gpio_request_one(cdata->gpio, flags,
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dev_name(&spi->dev));
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} else {
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if (spi->mode & SPI_CS_HIGH)
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@@ -148,7 +151,8 @@ static int ath79_spi_setup_cs(struct spi
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static void ath79_spi_cleanup_cs(struct spi_device *spi)
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{
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if (spi->chip_select) {
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- gpio_free(spi->cs_gpio);
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+ struct ath79_spi_controller_data *cdata = spi->controller_data;
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+ gpio_free(cdata->gpio);
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}
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}
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@@ -220,7 +224,6 @@ static int ath79_spi_probe(struct platfo
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}
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sp = spi_master_get_devdata(master);
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- master->dev.of_node = pdev->dev.of_node;
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platform_set_drvdata(pdev, sp);
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pdata = dev_get_platdata(&pdev->dev);
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@@ -300,18 +303,12 @@ static void ath79_spi_shutdown(struct pl
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ath79_spi_remove(pdev);
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}
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-static const struct of_device_id ath79_spi_of_match[] = {
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- { .compatible = "qca,ar7100-spi", },
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- { },
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-};
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-
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static struct platform_driver ath79_spi_driver = {
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.probe = ath79_spi_probe,
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.remove = ath79_spi_remove,
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.shutdown = ath79_spi_shutdown,
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.driver = {
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.name = DRV_NAME,
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- .of_match_table = ath79_spi_of_match,
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},
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};
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module_platform_driver(ath79_spi_driver);
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@ -0,0 +1,20 @@ |
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--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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@@ -14,6 +14,7 @@
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struct ath79_spi_platform_data {
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unsigned bus_num;
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unsigned num_chipselect;
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+ int *cs_gpios;
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};
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#endif /* _ATH79_SPI_PLATFORM_H */
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -231,6 +231,7 @@ static int ath79_spi_probe(struct platfo
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if (pdata) {
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->num_chipselect;
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+ master->cs_gpios = pdata->cs_gpios;
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}
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sp->bitbang.master = master;
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@ -0,0 +1,70 @@ |
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From: Felix Fietkau <nbd@nbd.name>
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Date: Fri, 9 Dec 2016 20:09:16 +0100
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Subject: [PATCH] spi: spi-ath79: support multiple internal chip select
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lines
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Several devices with multiple flash chips use the internal chip select
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lines. Don't assume that chip select 1 and above are GPIO lines.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -78,14 +78,16 @@ static void ath79_spi_chipselect(struct
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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- if (spi->chip_select) {
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+ if (gpio_is_valid(spi->cs_gpio)) {
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/* SPI is normally active-low */
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gpio_set_value(spi->cs_gpio, cs_high);
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} else {
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+ u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
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+
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if (cs_high)
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- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base |= cs_bit;
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else
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- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base &= ~cs_bit;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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@@ -118,11 +120,8 @@ static int ath79_spi_setup_cs(struct spi
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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int status;
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- if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
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- return -EINVAL;
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-
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status = 0;
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- if (spi->chip_select) {
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+ if (gpio_is_valid(spi->cs_gpio)) {
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unsigned long flags;
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flags = GPIOF_DIR_OUT;
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@@ -134,10 +133,12 @@ static int ath79_spi_setup_cs(struct spi
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status = gpio_request_one(spi->cs_gpio, flags,
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dev_name(&spi->dev));
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} else {
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+ u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
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+
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if (spi->mode & SPI_CS_HIGH)
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- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base &= ~cs_bit;
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else
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- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base |= cs_bit;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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@@ -147,7 +148,7 @@ static int ath79_spi_setup_cs(struct spi
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static void ath79_spi_cleanup_cs(struct spi_device *spi)
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{
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- if (spi->chip_select) {
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+ if (gpio_is_valid(spi->cs_gpio)) {
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gpio_free(spi->cs_gpio);
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}
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}
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@ -0,0 +1,19 @@ |
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From: Felix Fietkau <nbd@nbd.name>
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Date: Fri, 9 Dec 2016 20:11:35 +0100
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Subject: [PATCH] spi: spi-ath79: use gpio_set_value_cansleep for GPIO chip
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select
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -80,7 +80,7 @@ static void ath79_spi_chipselect(struct
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if (gpio_is_valid(spi->cs_gpio)) {
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/* SPI is normally active-low */
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- gpio_set_value(spi->cs_gpio, cs_high);
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+ gpio_set_value_cansleep(spi->cs_gpio, cs_high);
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} else {
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u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
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@ -1,199 +0,0 @@ |
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From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Wed, 11 Jan 2012 22:25:11 +0100
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Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/mach-pb44.c | 6 ++
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.../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++-
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drivers/spi/spi-ath79.c | 67 +++++++++++++-------
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8 files changed, 88 insertions(+), 23 deletions(-)
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--- a/arch/mips/ath79/mach-pb44.c
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+++ b/arch/mips/ath79/mach-pb44.c
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@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
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}
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};
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+static struct ath79_spi_controller_data pb44_spi0_data = {
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+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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+ .cs_line = 0,
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+};
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+
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static struct spi_board_info pb44_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p64",
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+ .controller_data = &pb44_spi0_data,
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},
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};
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--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
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unsigned num_chipselect;
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};
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+enum ath79_spi_cs_type {
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+ ATH79_SPI_CS_TYPE_INTERNAL,
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+ ATH79_SPI_CS_TYPE_GPIO,
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+};
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+
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struct ath79_spi_controller_data {
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- unsigned gpio;
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+ enum ath79_spi_cs_type cs_type;
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+ unsigned cs_line;
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};
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#endif /* _ATH79_SPI_PLATFORM_H */
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -33,6 +33,8 @@
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#define ATH79_SPI_RRW_DELAY_FACTOR 12000
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#define MHZ (1000 * 1000)
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+#define ATH79_SPI_CS_LINE_MAX 2
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+
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struct ath79_spi {
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struct spi_bitbang bitbang;
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u32 ioc_base;
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@@ -67,6 +69,7 @@ static void ath79_spi_chipselect(struct
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
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+ struct ath79_spi_controller_data *cdata = spi->controller_data;
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if (is_active) {
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/* set initial clock polarity */
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@@ -78,20 +81,24 @@ static void ath79_spi_chipselect(struct
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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- if (spi->chip_select) {
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- struct ath79_spi_controller_data *cdata = spi->controller_data;
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-
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- /* SPI is normally active-low */
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- gpio_set_value(cdata->gpio, cs_high);
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- } else {
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+ switch (cdata->cs_type) {
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+ case ATH79_SPI_CS_TYPE_INTERNAL:
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if (cs_high)
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- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
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else
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- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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- }
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+ break;
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+ case ATH79_SPI_CS_TYPE_GPIO:
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+ /* SPI is normally active-low */
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+ if (gpio_cansleep(cdata->cs_line))
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+ gpio_set_value_cansleep(cdata->cs_line, cs_high);
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+ else
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+ gpio_set_value(cdata->cs_line, cs_high);
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+ break;
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+ }
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}
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static void ath79_spi_enable(struct ath79_spi *sp)
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@@ -119,14 +126,15 @@ static int ath79_spi_setup_cs(struct spi
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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struct ath79_spi_controller_data *cdata = spi->controller_data;
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+ unsigned long flags;
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int status;
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- if (spi->chip_select && (!cdata || !gpio_is_valid(cdata->gpio)))
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+ if (!cdata)
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return -EINVAL;
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status = 0;
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- if (spi->chip_select) {
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- unsigned long flags;
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+ switch (cdata->cs_type) {
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+ case ATH79_SPI_CS_TYPE_GPIO:
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flags = GPIOF_DIR_OUT;
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if (spi->mode & SPI_CS_HIGH)
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@@ -134,15 +142,21 @@ static int ath79_spi_setup_cs(struct spi
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else
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flags |= GPIOF_INIT_HIGH;
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- status = gpio_request_one(cdata->gpio, flags,
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+ status = gpio_request_one(cdata->cs_line, flags,
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dev_name(&spi->dev));
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- } else {
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+ break;
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+ case ATH79_SPI_CS_TYPE_INTERNAL:
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+ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
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+ status = -EINVAL;
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+ break;
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+
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if (spi->mode & SPI_CS_HIGH)
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sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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else
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sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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+ break;
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}
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return status;
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@@ -150,9 +164,19 @@ static int ath79_spi_setup_cs(struct spi
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static void ath79_spi_cleanup_cs(struct spi_device *spi)
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{
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- if (spi->chip_select) {
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- struct ath79_spi_controller_data *cdata = spi->controller_data;
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- gpio_free(cdata->gpio);
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+ struct ath79_spi_controller_data *cdata;
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+
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+ cdata = spi->controller_data;
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+ if (!cdata)
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+ return;
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+
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+ switch (cdata->cs_type) {
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+ case ATH79_SPI_CS_TYPE_INTERNAL:
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+ /* nothing to do */
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+ break;
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+ case ATH79_SPI_CS_TYPE_GPIO:
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+ gpio_free(cdata->cs_line);
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+ break;
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}
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}
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@@ -217,6 +241,10 @@ static int ath79_spi_probe(struct platfo
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unsigned long rate;
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int ret;
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+ pdata = pdev->dev.platform_data;
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+ if (!pdata)
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+ return -EINVAL;
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+
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master = spi_alloc_master(&pdev->dev, sizeof(*sp));
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if (master == NULL) {
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dev_err(&pdev->dev, "failed to allocate spi master\n");
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@@ -226,15 +254,11 @@ static int ath79_spi_probe(struct platfo
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sp = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, sp);
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- pdata = dev_get_platdata(&pdev->dev);
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-
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
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master->setup = ath79_spi_setup;
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master->cleanup = ath79_spi_cleanup;
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- if (pdata) {
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- master->bus_num = pdata->bus_num;
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- master->num_chipselect = pdata->num_chipselect;
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- }
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+ master->bus_num = pdata->bus_num;
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+ master->num_chipselect = pdata->num_chipselect;
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sp->bitbang.master = master;
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sp->bitbang.chipselect = ath79_spi_chipselect;
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@ -0,0 +1,15 @@ |
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--- a/drivers/mtd/devices/m25p80.c
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+++ b/drivers/mtd/devices/m25p80.c
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@@ -149,8 +149,10 @@ static int m25p80_read(struct spi_nor *n
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msg.data_nbits = m25p80_rx_nbits(nor);
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ret = spi_flash_read(spi, &msg);
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- *retlen = msg.retlen;
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- return ret;
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+ if (!ret) {
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+ *retlen = msg.retlen;
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+ return 0;
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+ }
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}
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spi_message_init(&m);
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@ -1,28 +0,0 @@ |
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--- a/drivers/spi/spi-bitbang.c
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+++ b/drivers/spi/spi-bitbang.c
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@@ -231,13 +231,14 @@ void spi_bitbang_cleanup(struct spi_devi
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}
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EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
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-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
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+int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct spi_bitbang_cs *cs = spi->controller_state;
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unsigned nsecs = cs->nsecs;
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|
||||
return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
--- a/include/linux/spi/spi_bitbang.h
|
||||
+++ b/include/linux/spi/spi_bitbang.h
|
||||
@@ -39,6 +39,7 @@ extern int spi_bitbang_setup(struct spi_
|
||||
extern void spi_bitbang_cleanup(struct spi_device *spi);
|
||||
extern int spi_bitbang_setup_transfer(struct spi_device *spi,
|
||||
struct spi_transfer *t);
|
||||
+extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
|
||||
|
||||
/* start or stop queue processing */
|
||||
extern int spi_bitbang_start(struct spi_bitbang *spi);
|
||||
@ -1,23 +0,0 @@ |
||||
--- a/include/linux/spi/spi.h
|
||||
+++ b/include/linux/spi/spi.h
|
||||
@@ -583,6 +583,12 @@ extern struct spi_master *spi_busnum_to_
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
+enum spi_transfer_type {
|
||||
+ SPI_TRANSFER_GENERIC = 0,
|
||||
+ SPI_TRANSFER_FLASH_READ_CMD,
|
||||
+ SPI_TRANSFER_FLASH_READ_DATA,
|
||||
+};
|
||||
+
|
||||
/*
|
||||
* I/O INTERFACE between SPI controller and protocol drivers
|
||||
*
|
||||
@@ -703,6 +709,7 @@ struct spi_transfer {
|
||||
u8 bits_per_word;
|
||||
u16 delay_usecs;
|
||||
u32 speed_hz;
|
||||
+ enum spi_transfer_type type;
|
||||
|
||||
struct list_head transfer_list;
|
||||
};
|
||||
@ -0,0 +1,54 @@ |
||||
--- a/drivers/spi/spi-ath79.c
|
||||
+++ b/drivers/spi/spi-ath79.c
|
||||
@@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7
|
||||
/* save CTRL register */
|
||||
sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
|
||||
sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
|
||||
-
|
||||
- /* TODO: setup speed? */
|
||||
- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
|
||||
}
|
||||
|
||||
static void ath79_spi_disable(struct ath79_spi *sp)
|
||||
@@ -205,6 +202,33 @@ static u32 ath79_spi_txrx_mode0(struct s
|
||||
return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
|
||||
}
|
||||
|
||||
+static int ath79_spi_read_flash_data(struct spi_device *spi,
|
||||
+ struct spi_flash_read_message *msg)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+
|
||||
+ if (msg->addr_width > 3)
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
+ if (spi->chip_select || gpio_is_valid(spi->cs_gpio))
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
+ /* disable GPIO mode */
|
||||
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
|
||||
+
|
||||
+ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len);
|
||||
+
|
||||
+ /* enable GPIO mode */
|
||||
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
|
||||
+
|
||||
+ /* restore IOC register */
|
||||
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
|
||||
+
|
||||
+ msg->retlen = msg->len;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int ath79_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
@@ -234,6 +258,7 @@ static int ath79_spi_probe(struct platfo
|
||||
master->num_chipselect = pdata->num_chipselect;
|
||||
master->cs_gpios = pdata->cs_gpios;
|
||||
}
|
||||
+ master->spi_flash_read = ath79_spi_read_flash_data;
|
||||
|
||||
sp->bitbang.master = master;
|
||||
sp->bitbang.chipselect = ath79_spi_chipselect;
|
||||
@ -1,15 +0,0 @@ |
||||
--- a/drivers/mtd/devices/m25p80.c
|
||||
+++ b/drivers/mtd/devices/m25p80.c
|
||||
@@ -159,10 +159,12 @@ static int m25p80_read(struct spi_nor *n
|
||||
flash->command[0] = nor->read_opcode;
|
||||
m25p_addr2cmd(nor, from, flash->command);
|
||||
|
||||
+ t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
|
||||
t[0].tx_buf = flash->command;
|
||||
t[0].len = m25p_cmdsz(nor) + dummy;
|
||||
spi_message_add_tail(&t[0], &m);
|
||||
|
||||
+ t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
|
||||
t[1].rx_buf = buf;
|
||||
t[1].rx_nbits = m25p80_rx_nbits(nor);
|
||||
t[1].len = len;
|
||||
@ -1,185 +0,0 @@ |
||||
--- a/drivers/spi/spi-ath79.c
|
||||
+++ b/drivers/spi/spi-ath79.c
|
||||
@@ -35,6 +35,11 @@
|
||||
|
||||
#define ATH79_SPI_CS_LINE_MAX 2
|
||||
|
||||
+enum ath79_spi_state {
|
||||
+ ATH79_SPI_STATE_WAIT_CMD = 0,
|
||||
+ ATH79_SPI_STATE_WAIT_READ,
|
||||
+};
|
||||
+
|
||||
struct ath79_spi {
|
||||
struct spi_bitbang bitbang;
|
||||
u32 ioc_base;
|
||||
@@ -42,6 +47,11 @@ struct ath79_spi {
|
||||
void __iomem *base;
|
||||
struct clk *clk;
|
||||
unsigned rrw_delay;
|
||||
+
|
||||
+ enum ath79_spi_state state;
|
||||
+ u32 clk_div;
|
||||
+ unsigned long read_addr;
|
||||
+ unsigned long ahb_rate;
|
||||
};
|
||||
|
||||
static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
|
||||
@@ -109,9 +119,6 @@ static void ath79_spi_enable(struct ath7
|
||||
/* save CTRL register */
|
||||
sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
|
||||
sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
|
||||
-
|
||||
- /* TODO: setup speed? */
|
||||
- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
|
||||
}
|
||||
|
||||
static void ath79_spi_disable(struct ath79_spi *sp)
|
||||
@@ -232,6 +239,110 @@ static u32 ath79_spi_txrx_mode0(struct s
|
||||
return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
|
||||
}
|
||||
|
||||
+static int ath79_spi_do_read_flash_data(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+
|
||||
+ /* disable GPIO mode */
|
||||
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
|
||||
+
|
||||
+ memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
|
||||
+
|
||||
+ /* enable GPIO mode */
|
||||
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
|
||||
+
|
||||
+ /* restore IOC register */
|
||||
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
|
||||
+
|
||||
+ return t->len;
|
||||
+}
|
||||
+
|
||||
+static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+ int len;
|
||||
+ const u8 *p;
|
||||
+
|
||||
+ sp->read_addr = 0;
|
||||
+
|
||||
+ len = t->len - 1;
|
||||
+ p = t->tx_buf;
|
||||
+
|
||||
+ while (len--) {
|
||||
+ p++;
|
||||
+ sp->read_addr <<= 8;
|
||||
+ sp->read_addr |= *p;
|
||||
+ }
|
||||
+
|
||||
+ return t->len;
|
||||
+}
|
||||
+
|
||||
+static bool ath79_spi_is_read_cmd(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ return t->type == SPI_TRANSFER_FLASH_READ_CMD;
|
||||
+}
|
||||
+
|
||||
+static bool ath79_spi_is_data_read(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ return t->type == SPI_TRANSFER_FLASH_READ_DATA;
|
||||
+}
|
||||
+
|
||||
+static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+ int ret;
|
||||
+
|
||||
+ switch (sp->state) {
|
||||
+ case ATH79_SPI_STATE_WAIT_CMD:
|
||||
+ if (ath79_spi_is_read_cmd(spi, t)) {
|
||||
+ ret = ath79_spi_do_read_flash_cmd(spi, t);
|
||||
+ sp->state = ATH79_SPI_STATE_WAIT_READ;
|
||||
+ } else {
|
||||
+ ret = spi_bitbang_bufs(spi, t);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ case ATH79_SPI_STATE_WAIT_READ:
|
||||
+ if (ath79_spi_is_data_read(spi, t)) {
|
||||
+ ret = ath79_spi_do_read_flash_data(spi, t);
|
||||
+ } else {
|
||||
+ dev_warn(&spi->dev, "flash data read expected\n");
|
||||
+ ret = -EIO;
|
||||
+ }
|
||||
+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ BUG();
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int ath79_spi_setup_transfer(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+ struct ath79_spi_controller_data *cdata;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = spi_bitbang_setup_transfer(spi, t);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ cdata = spi->controller_data;
|
||||
+ if (cdata->is_flash)
|
||||
+ sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
|
||||
+ else
|
||||
+ sp->bitbang.txrx_bufs = spi_bitbang_bufs;
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
static int ath79_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
@@ -254,6 +365,8 @@ static int ath79_spi_probe(struct platfo
|
||||
sp = spi_master_get_devdata(master);
|
||||
platform_set_drvdata(pdev, sp);
|
||||
|
||||
+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
|
||||
+
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
||||
master->setup = ath79_spi_setup;
|
||||
master->cleanup = ath79_spi_cleanup;
|
||||
@@ -263,7 +376,7 @@ static int ath79_spi_probe(struct platfo
|
||||
sp->bitbang.master = master;
|
||||
sp->bitbang.chipselect = ath79_spi_chipselect;
|
||||
sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
|
||||
- sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
|
||||
+ sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
|
||||
sp->bitbang.flags = SPI_CS_HIGH;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
@@ -283,7 +396,8 @@ static int ath79_spi_probe(struct platfo
|
||||
if (ret)
|
||||
goto err_put_master;
|
||||
|
||||
- rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
|
||||
+ sp->ahb_rate = clk_get_rate(sp->clk);
|
||||
+ rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
|
||||
if (!rate) {
|
||||
ret = -EINVAL;
|
||||
goto err_clk_disable;
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
@@ -24,6 +24,7 @@ enum ath79_spi_cs_type {
|
||||
struct ath79_spi_controller_data {
|
||||
enum ath79_spi_cs_type cs_type;
|
||||
unsigned cs_line;
|
||||
+ bool is_flash;
|
||||
};
|
||||
|
||||
#endif /* _ATH79_SPI_PLATFORM_H */
|
||||
@ -1,35 +0,0 @@ |
||||
--- a/drivers/mtd/devices/m25p80.c
|
||||
+++ b/drivers/mtd/devices/m25p80.c
|
||||
@@ -159,6 +159,9 @@ static int m25p80_read(struct spi_nor *n
|
||||
flash->command[0] = nor->read_opcode;
|
||||
m25p_addr2cmd(nor, from, flash->command);
|
||||
|
||||
+ if (dummy == 1)
|
||||
+ t[0].dummy = true;
|
||||
+
|
||||
t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
|
||||
t[0].tx_buf = flash->command;
|
||||
t[0].len = m25p_cmdsz(nor) + dummy;
|
||||
--- a/drivers/spi/spi-ath79.c
|
||||
+++ b/drivers/spi/spi-ath79.c
|
||||
@@ -268,6 +268,10 @@ static int ath79_spi_do_read_flash_cmd(s
|
||||
sp->read_addr = 0;
|
||||
|
||||
len = t->len - 1;
|
||||
+
|
||||
+ if (t->dummy)
|
||||
+ len -= 1;
|
||||
+
|
||||
p = t->tx_buf;
|
||||
|
||||
while (len--) {
|
||||
--- a/include/linux/spi/spi.h
|
||||
+++ b/include/linux/spi/spi.h
|
||||
@@ -710,6 +710,7 @@ struct spi_transfer {
|
||||
u16 delay_usecs;
|
||||
u32 speed_hz;
|
||||
enum spi_transfer_type type;
|
||||
+ bool dummy;
|
||||
|
||||
struct list_head transfer_list;
|
||||
};
|
||||
Loading…
Reference in new issue