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@ -93,7 +93,7 @@ |
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#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@@ -252,6 +278,8 @@
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@@ -252,9 +278,13 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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@ -102,7 +102,12 @@ |
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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@@ -378,16 +406,50 @@
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+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
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+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@@ -378,16 +408,83 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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@ -147,13 +152,46 @@ |
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+#define AR934X_RESET_LUT BIT(2)
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+#define AR934X_RESET_MBOX BIT(1)
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+#define AR934X_RESET_I2S BIT(0)
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+
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+#define QCA955X_RESET_HOST BIT(31)
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+#define QCA955X_RESET_SLIC BIT(30)
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+#define QCA955X_RESET_HDMA BIT(29)
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+#define QCA955X_RESET_EXTERNAL BIT(28)
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+#define QCA955X_RESET_RTC BIT(27)
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+#define QCA955X_RESET_PCIE_EP_INT BIT(26)
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+#define QCA955X_RESET_CHKSUM_ACC BIT(25)
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+#define QCA955X_RESET_FULL_CHIP BIT(24)
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+#define QCA955X_RESET_GE1_MDIO BIT(23)
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+#define QCA955X_RESET_GE0_MDIO BIT(22)
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+#define QCA955X_RESET_CPU_NMI BIT(21)
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+#define QCA955X_RESET_CPU_COLD BIT(20)
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+#define QCA955X_RESET_HOST_RESET_INT BIT(19)
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+#define QCA955X_RESET_PCIE_EP BIT(18)
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+#define QCA955X_RESET_UART1 BIT(17)
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+#define QCA955X_RESET_DDR BIT(16)
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+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
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+#define QCA955X_RESET_NANDF BIT(14)
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+#define QCA955X_RESET_GE1_MAC BIT(13)
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+#define QCA955X_RESET_SGMII_ANALOG BIT(12)
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+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
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+#define QCA955X_RESET_HOST_DMA_INT BIT(10)
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+#define QCA955X_RESET_GE0_MAC BIT(9)
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+#define QCA955X_RESET_SGMII BIT(8)
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+#define QCA955X_RESET_PCIE_PHY BIT(7)
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+#define QCA955X_RESET_PCIE BIT(6)
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+#define QCA955X_RESET_USB_HOST BIT(5)
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+#define QCA955X_RESET_USB_PHY BIT(4)
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+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
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+#define QCA955X_RESET_LUT BIT(2)
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+#define QCA955X_RESET_MBOX BIT(1)
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+#define QCA955X_RESET_I2S BIT(0)
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+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
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+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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@@ -528,6 +590,12 @@
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@@ -528,6 +625,12 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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@ -166,7 +204,7 @@ |
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#define AR934X_GPIO_REG_FUNC 0x6c
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#define AR71XX_GPIO_COUNT 16
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@@ -559,4 +627,133 @@
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@@ -559,4 +662,133 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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