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ar71xx: fix NAND controller base for QCA955x SoCs

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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34942
master
Gabor Juhos 12 years ago
parent b57cc9a538
commit 93c322cacc
2 changed files with 2 additions and 2 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
  2. 2
      target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch

2
target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
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@ -50,7 +50,7 @@
#define QCA955X_EHCI_SIZE 0x200
+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE 0x40
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_BASE 0x1b800200
+#define QCA955X_NFC_SIZE 0xb8
#define AR9300_OTP_BASE 0x14000

2
target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch
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@ -48,7 +48,7 @@
#define QCA955X_EHCI_SIZE 0x200
+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE 0x40
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_BASE 0x1b800200
+#define QCA955X_NFC_SIZE 0xb8
#define AR9300_OTP_BASE 0x14000

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