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@ -16,6 +16,8 @@ |
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#include <mach/mcs814x.h> |
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#include <mach/mcs814x.h> |
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#include "common.h" |
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#define KHZ 1000 |
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#define KHZ 1000 |
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#define MHZ (KHZ * KHZ) |
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#define MHZ (KHZ * KHZ) |
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@ -32,7 +34,7 @@ struct clk { |
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unsigned long divider; /* clock divider */ |
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unsigned long divider; /* clock divider */ |
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u32 usecount; /* reference count */ |
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u32 usecount; /* reference count */ |
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struct clk_ops *ops; /* clock operation */ |
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struct clk_ops *ops; /* clock operation */ |
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void __iomem *enable_reg; /* clock enable register */ |
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u32 enable_reg; /* clock enable register */ |
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u32 enable_mask; /* clock enable mask */ |
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u32 enable_mask; /* clock enable mask */ |
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}; |
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}; |
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@ -52,13 +54,13 @@ static int clk_local_onoff_enable(struct clk *clk, int enable) |
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if (!clk->enable_reg) |
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if (!clk->enable_reg) |
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return 0; |
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return 0; |
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tmp = __raw_readl(clk->enable_reg); |
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tmp = __raw_readl(mcs814x_sysdbg_base + clk->enable_reg); |
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if (!enable) |
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if (!enable) |
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tmp &= ~clk->enable_mask; |
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tmp &= ~clk->enable_mask; |
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else |
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else |
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tmp |= clk->enable_mask; |
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tmp |= clk->enable_mask; |
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__raw_writel(tmp, clk->enable_reg); |
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__raw_writel(tmp, mcs814x_sysdbg_base + clk->enable_reg); |
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return 0; |
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return 0; |
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} |
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} |
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@ -117,19 +119,19 @@ static struct clk clk_wdt = { |
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static struct clk clk_emac = { |
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static struct clk clk_emac = { |
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.ops = &default_clk_ops, |
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.ops = &default_clk_ops, |
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.enable_reg = (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_SYSCTL), |
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.enable_reg = SYSDBG_SYSCTL, |
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.enable_mask = SYSCTL_EMAC, |
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.enable_mask = SYSCTL_EMAC, |
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}; |
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}; |
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static struct clk clk_ephy = { |
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static struct clk clk_ephy = { |
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.ops = &default_clk_ops, |
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.ops = &default_clk_ops, |
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.enable_reg = (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_PLL_CTL), |
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.enable_reg = SYSDBG_PLL_CTL, |
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.enable_mask = ~(1 << 0), |
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.enable_mask = ~SYSCTL_EPHY, /* active low */ |
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}; |
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}; |
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static struct clk clk_cipher = { |
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static struct clk clk_cipher = { |
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.ops = &default_clk_ops, |
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.ops = &default_clk_ops, |
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.enable_reg = (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_SYSCTL), |
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.enable_reg = SYSDBG_SYSCTL, |
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.enable_mask = SYSCTL_CIPHER, |
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.enable_mask = SYSCTL_CIPHER, |
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}; |
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}; |
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@ -252,7 +254,7 @@ void __init mcs814x_clk_init(void) |
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clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks)); |
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clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks)); |
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/* read the bootstrap registers to know the exact clocking scheme */ |
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/* read the bootstrap registers to know the exact clocking scheme */ |
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bs1 = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS1); |
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bs1 = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS1); |
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cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK; |
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cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK; |
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pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]); |
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pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]); |
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