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@ -69,6 +69,18 @@ static void ag71xx_dump_regs(struct ag71xx *ag) |
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); |
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); |
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} |
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} |
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static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) |
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{ |
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DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", |
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ag->dev->name, label, intr, |
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(intr & AG71XX_INT_TX_PS) ? "TXPS " : "", |
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(intr & AG71XX_INT_TX_UR) ? "TXUR " : "", |
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(intr & AG71XX_INT_TX_BE) ? "TXBE " : "", |
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(intr & AG71XX_INT_RX_PR) ? "RXPR " : "", |
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(intr & AG71XX_INT_RX_OF) ? "RXOF " : "", |
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(intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); |
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} |
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static void ag71xx_ring_free(struct ag71xx_ring *ring) |
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static void ag71xx_ring_free(struct ag71xx_ring *ring) |
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{ |
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{ |
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kfree(ring->buf); |
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kfree(ring->buf); |
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@ -315,6 +327,14 @@ static void ag71xx_dma_reset(struct ag71xx *ag) |
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); |
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); |
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); |
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); |
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if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS)) |
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printk(KERN_ALERT "%s: unable to clear DMA Rx status\n", |
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ag->dev->name); |
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if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS)) |
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printk(KERN_ALERT "%s: unable to clear DMA Tx status\n", |
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ag->dev->name); |
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ag71xx_dump_dma_regs(ag); |
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ag71xx_dump_dma_regs(ag); |
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} |
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} |
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@ -693,7 +713,9 @@ static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) |
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u32 status; |
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u32 status; |
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status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); |
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status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); |
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ag71xx_dump_intr(ag, "raw", status); |
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status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE); |
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status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE); |
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ag71xx_dump_intr(ag, "masked", status); |
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if (unlikely(!status)) |
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if (unlikely(!status)) |
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return IRQ_NONE; |
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return IRQ_NONE; |
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