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@ -28,6 +28,21 @@ static int ag71xx_debug = -1; |
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module_param(ag71xx_debug, int, 0); |
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MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)"); |
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static void ag71xx_dump_dma_regs(struct ag71xx *ag) |
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{ |
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DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", |
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ag->dev->name, |
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ag71xx_rr(ag, AG71XX_REG_TX_CTRL), |
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ag71xx_rr(ag, AG71XX_REG_TX_DESC), |
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ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); |
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DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", |
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ag->dev->name, |
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ag71xx_rr(ag, AG71XX_REG_RX_CTRL), |
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ag71xx_rr(ag, AG71XX_REG_RX_DESC), |
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ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); |
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} |
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static void ag71xx_dump_regs(struct ag71xx *ag) |
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{ |
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DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", |
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@ -276,6 +291,33 @@ static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) |
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#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) |
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static void ag71xx_dma_reset(struct ag71xx *ag) |
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{ |
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int i; |
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ag71xx_dump_dma_regs(ag); |
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/* stop RX and TX */ |
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); |
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ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); |
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/* clear descriptor addresses */ |
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0); |
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ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0); |
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/* clear pending RX/TX interrupts */ |
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for (i = 0; i < 256; i++) { |
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); |
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); |
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} |
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/* clear pending errors */ |
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); |
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); |
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ag71xx_dump_dma_regs(ag); |
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} |
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static void ag71xx_hw_init(struct ag71xx *ag) |
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{ |
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
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@ -288,9 +330,6 @@ static void ag71xx_hw_init(struct ag71xx *ag) |
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ar71xx_device_start(pdata->reset_bit); |
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mdelay(100); |
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/* setup MII interface type */ |
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ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); |
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/* setup MAC configuration registers */ |
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, |
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pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT); |
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@ -300,6 +339,9 @@ static void ag71xx_hw_init(struct ag71xx *ag) |
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/* setup max frame length */ |
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ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); |
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/* setup MII interface type */ |
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ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); |
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/* setup FIFO configuration registers */ |
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); |
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); |
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@ -308,6 +350,8 @@ static void ag71xx_hw_init(struct ag71xx *ag) |
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, |
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pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT |
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: AR71XX_FIFO_CFG5_INIT); |
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ag71xx_dma_reset(ag); |
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} |
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static void ag71xx_hw_start(struct ag71xx *ag) |
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@ -321,12 +365,10 @@ static void ag71xx_hw_start(struct ag71xx *ag) |
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static void ag71xx_hw_stop(struct ag71xx *ag) |
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{ |
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/* stop RX and TX */ |
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); |
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ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); |
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/* disable all interrupts */ |
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); |
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ag71xx_dma_reset(ag); |
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} |
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static int ag71xx_open(struct net_device *dev) |
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