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@ -25,19 +25,14 @@ |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <asm/io.h> |
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#include <asm/bootinfo.h> |
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#include <asm/addrspace.h> |
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#include <asm/mach-adm5120/adm5120_info.h> |
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#include <asm/mach-adm5120/adm5120_defs.h> |
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#include <asm/mach-adm5120/adm5120_switch.h> |
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#include <asm/mach-adm5120/adm5120_mpmc.h> |
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#define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r)) |
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#define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v) |
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#define MPMC_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r)) |
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#define MPMC_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v) |
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#include <adm5120_info.h> |
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#include <adm5120_defs.h> |
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#include <adm5120_switch.h> |
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#include <adm5120_mpmc.h> |
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#if 1 |
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# define mem_dbg(f, a...) printk("mem_detect: " f, ## a) |
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@ -45,19 +40,19 @@ |
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# define mem_dbg(f, a...) |
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#endif |
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#define MEM_WR_DELAY 10000 /* 0.01 usec */ |
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unsigned long adm5120_memsize; |
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#define MEM_READL(a) __raw_readl((void __iomem *)(a)) |
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#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a)) |
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static int __init mem_check_pattern(u8 *addr, unsigned long offs) |
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{ |
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volatile u32 *p1 = (volatile u32 *)addr; |
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volatile u32 *p2 = (volatile u32 *)(addr+offs); |
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u32 *p1 = (u32 *)addr; |
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u32 *p2 = (u32 *)(addr+offs); |
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u32 t,u,v; |
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/* save original value */ |
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t = *p1; |
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u = *p2; |
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t = MEM_READL(p1); |
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u = MEM_READL(p2); |
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if (t != u) |
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return 0; |
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@ -68,15 +63,17 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs) |
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mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1); |
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*p1 = v; |
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mem_dbg("delay %d ns\n", MEM_WR_DELAY); |
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adm5120_ndelay(MEM_WR_DELAY); |
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u = *p2; |
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MEM_WRITEL(p1, v); |
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/* flush write buffers */ |
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MPMC_WRITE_REG(CTRL, MPMC_READ_REG(CTRL) | MPMC_CTRL_DWB); |
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u = MEM_READL(p2); |
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mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u); |
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/* restore original value */ |
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*p1 = t; |
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MEM_WRITEL(p1, t); |
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return (v == u); |
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} |
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@ -87,7 +84,7 @@ static void __init adm5120_detect_memsize(void) |
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u32 size, maxsize; |
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u8 *p; |
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memctrl = SWITCH_READ(SWITCH_REG_MEMCTRL); |
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memctrl = SW_READ_REG(MEMCTRL); |
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switch (memctrl & MEMCTRL_SDRS_MASK) { |
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case MEMCTRL_SDRS_4M: |
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maxsize = 4 << 20; |
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@ -103,11 +100,6 @@ static void __init adm5120_detect_memsize(void) |
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break; |
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} |
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/* disable buffers for both SDRAM banks */ |
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mem_dbg("disable buffers for both banks\n"); |
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MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) & ~DC_BE); |
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MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) & ~DC_BE); |
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mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20); |
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/* detect size of the 1st SDRAM bank */ |
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@ -159,15 +151,10 @@ static void __init adm5120_detect_memsize(void) |
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memctrl |= MEMCTRL_SDRS_64M; |
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break; |
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} |
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SWITCH_WRITE(SWITCH_REG_MEMCTRL, memctrl); |
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SW_WRITE_REG(MEMCTRL, memctrl); |
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} |
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out: |
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/* reenable buffer for both SDRAM banks */ |
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mem_dbg("enable buffers for both banks\n"); |
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MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) | DC_BE); |
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MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) | DC_BE); |
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mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 , |
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size >>20); |
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} |
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