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@ -72,6 +72,8 @@ |
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#define GSW_REG_IMR 0x7008 |
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#define GSW_REG_ISR 0x700c |
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#define GSW_REG_GPC1 0x7014 |
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#define GSW_PHY1_DISABLE BIT(25) |
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#define SYSC_REG_CFG1 0x14 |
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@ -414,6 +416,8 @@ static void gsw_hw_init(struct mt7620_gsw *gsw) |
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rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1); |
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gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR); |
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/* EPHY1 fixup - only run if the ephy is enabled */ |
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if (gsw_r32(gsw, GSW_REG_GPC1) & GSW_PHY1_DISABLE == GSW_PHY1_DISABLE) { |
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/*correct PHY setting L3.0 BGA*/ |
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_mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
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@ -451,6 +455,7 @@ static void gsw_hw_init(struct mt7620_gsw *gsw) |
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} |
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_mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
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_mt7620_mii_write(gsw, 1, 17, 0xe7f8); |
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} |
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_mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
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_mt7620_mii_write(gsw, 0, 30, 0xa000); |
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