Merge pull request #195 from harshavardhana/pr_out_add_license_header_for_minio_modifications_improvements_for_sha1_sha256_sha512_implementations
Harshavardhana
10 years ago
commit
87bca64173
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*.syso |
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Apache License |
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@ -0,0 +1,579 @@ |
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;--------------------- |
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; https://software.intel.com/en-us/articles/improving-the-performance-of-the-secure-hash-algorithm-1 |
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; |
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; License information: |
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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; This implementation notably advances the performance of SHA-1 algorithm compared to existing |
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; implementations. We are encouraging all projects utilizing SHA-1 to integrate this new fast |
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; implementation and are ready to help if issues or concerns arise (you are welcome to leave |
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; a comment or write an email to the authors). It is provided 'as is' and free for either |
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; commercial or non-commercial use. |
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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; |
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; This code implements two interfaces of SHA-1 update function: 1) working on a single |
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; 64-byte block and 2) working on a buffer of multiple 64-bit blocks. Multiple blocks |
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; version of code is software pipelined and faster overall, it is a default. Assemble |
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; with -DINTEL_SHA1_SINGLEBLOCK to select single 64-byte block function interface. |
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; |
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; C++ prototypes of implemented functions are below: |
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; |
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; #ifndef INTEL_SHA1_SINGLEBLOCK |
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; // Updates 20-byte SHA-1 record in 'hash' for 'num_blocks' consequtive 64-byte blocks |
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; extern "C" void sha1_update_intel(int *hash, const char* input, size_t num_blocks ); |
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; #else |
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; // Updates 20-byte SHA-1 record in 'hash' for one 64-byte block pointed by 'input' |
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; extern "C" void sha1_update_intel(int *hash, const char* input); |
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; #endif |
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; |
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; Function name 'sha1_update_intel' can be changed in the source or via macro: |
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; -DINTEL_SHA1_UPDATE_FUNCNAME=my_sha1_update_func_name |
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; |
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; It implements both UNIX(default) and Windows ABIs, use -DWIN_ABI on Windows |
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; |
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; Code checks CPU for SSSE3 support via CPUID feature flag (CPUID.1.ECX.SSSE3[bit 9]==1), |
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; and performs dispatch. Since in most cases the functionality on non-SSSE3 supporting CPUs |
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; is also required, the default (e.g. one being replaced) function can be provided for |
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; dispatch on such CPUs, the name of old function can be changed in the source or via macro: |
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; -DINTEL_SHA1_UPDATE_DEFAULT_DISPATCH=default_sha1_update_function_name |
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; |
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; Authors: Maxim Locktyukhin and Ronen Zohar at Intel.com |
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; |
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|
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%ifndef INTEL_SHA1_UPDATE_DEFAULT_DISPATCH |
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;; can be replaced with a default SHA-1 update function name |
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%define INTEL_SHA1_UPDATE_DEFAULT_DISPATCH sha1_intel_non_ssse3_cpu_stub_ |
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%else |
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extern INTEL_SHA1_UPDATE_DEFAULT_DISPATCH |
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%endif |
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|
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;; provide alternative SHA-1 update function's name here |
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%ifndef INTEL_SHA1_UPDATE_FUNCNAME |
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%define INTEL_SHA1_UPDATE_FUNCNAME sha1_update_intel |
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%endif |
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global INTEL_SHA1_UPDATE_FUNCNAME |
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%ifndef INTEL_SHA1_SINGLEBLOCK |
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%assign multiblock 1 |
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%else |
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%assign multiblock 0 |
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%endif |
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|
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bits 64 |
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default rel |
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|
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%ifdef WIN_ABI |
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%xdefine arg1 rcx |
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%xdefine arg2 rdx |
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%xdefine arg3 r8 |
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%else |
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%xdefine arg1 rdi |
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%xdefine arg2 rsi |
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%xdefine arg3 rdx |
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%endif |
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|
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%xdefine ctx arg1 |
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%xdefine buf arg2 |
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%xdefine cnt arg3 |
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|
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%macro REGALLOC 0 |
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%xdefine A ecx |
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%xdefine B esi |
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%xdefine C edi |
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%xdefine D ebp |
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%xdefine E edx |
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|
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%xdefine T1 eax |
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%xdefine T2 ebx |
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%endmacro |
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%xdefine K_BASE r8 |
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%xdefine HASH_PTR r9 |
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%xdefine BUFFER_PTR r10 |
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%xdefine BUFFER_END r11 |
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|
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%xdefine W_TMP xmm0 |
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%xdefine W_TMP2 xmm9 |
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|
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%xdefine W0 xmm1 |
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%xdefine W4 xmm2 |
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%xdefine W8 xmm3 |
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%xdefine W12 xmm4 |
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%xdefine W16 xmm5 |
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%xdefine W20 xmm6 |
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%xdefine W24 xmm7 |
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%xdefine W28 xmm8 |
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%xdefine XMM_SHUFB_BSWAP xmm10 |
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;; we keep window of 64 w[i]+K pre-calculated values in a circular buffer |
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%xdefine WK(t) (rsp + (t & 15)*4) |
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;------------------------------------------------------------------------------ |
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; |
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; macro implements SHA-1 function's body for single or several 64-byte blocks |
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; first param: function's name |
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; second param: =0 - function implements single 64-byte block hash |
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; =1 - function implements multiple64-byte blocks hash |
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; 3rd function's argument is a number, greater 0, of 64-byte blocks to calc hash for |
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; |
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%macro SHA1_VECTOR_ASM 2 |
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align 4096 |
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%1: |
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push rbx |
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push rbp |
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%ifdef WIN_ABI |
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push rdi |
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push rsi |
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%xdefine stack_size (16*4 + 16*5 + 8) |
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%else |
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%xdefine stack_size (16*4 + 8) |
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%endif |
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sub rsp, stack_size |
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%ifdef WIN_ABI |
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%xdefine xmm_save_base (rsp + 16*4) |
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xmm_mov [xmm_save_base + 0*16], xmm6 |
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xmm_mov [xmm_save_base + 1*16], xmm7 |
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xmm_mov [xmm_save_base + 2*16], xmm8 |
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xmm_mov [xmm_save_base + 3*16], xmm9 |
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xmm_mov [xmm_save_base + 4*16], xmm10 |
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%endif |
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mov HASH_PTR, ctx |
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mov BUFFER_PTR, buf |
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%if (%2 == 1) |
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shl cnt, 6 ;; mul by 64 |
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add cnt, buf |
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mov BUFFER_END, cnt |
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%endif |
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lea K_BASE, [K_XMM_AR] |
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xmm_mov XMM_SHUFB_BSWAP, [bswap_shufb_ctl] |
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|
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SHA1_PIPELINED_MAIN_BODY %2 |
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%ifdef WIN_ABI |
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xmm_mov xmm6, [xmm_save_base + 0*16] |
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xmm_mov xmm7, [xmm_save_base + 1*16] |
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xmm_mov xmm8, [xmm_save_base + 2*16] |
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xmm_mov xmm9, [xmm_save_base + 3*16] |
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xmm_mov xmm10,[xmm_save_base + 4*16] |
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%endif |
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|
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add rsp, stack_size |
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|
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%ifdef WIN_ABI |
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pop rsi |
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pop rdi |
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%endif |
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|
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pop rbp |
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pop rbx |
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ret |
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%endmacro |
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|
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;-------------------------------------------- |
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; macro implements 80 rounds of SHA-1, for one 64-byte block or multiple blocks with s/w pipelining |
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; macro param: =0 - process single 64-byte block |
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; =1 - multiple blocks |
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; |
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%macro SHA1_PIPELINED_MAIN_BODY 1 |
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REGALLOC |
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|
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mov A, [HASH_PTR ] |
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mov B, [HASH_PTR+ 4] |
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mov C, [HASH_PTR+ 8] |
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mov D, [HASH_PTR+12] |
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|
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mov E, [HASH_PTR+16] |
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|
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%assign i 0 |
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%rep W_PRECALC_AHEAD |
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W_PRECALC i |
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%assign i i+1 |
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%endrep |
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|
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%xdefine F F1 |
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|
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%if (%1 == 1) ;; code loops through more than one block |
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%%_loop: |
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cmp BUFFER_PTR, K_BASE ;; we use K_BASE value as a signal of a last block, |
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jne %%_begin ;; it is set below by: cmovae BUFFER_PTR, K_BASE |
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jmp %%_end |
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|
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align 32 |
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%%_begin: |
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%endif |
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RR A,B,C,D,E,0 |
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RR D,E,A,B,C,2 |
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RR B,C,D,E,A,4 |
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RR E,A,B,C,D,6 |
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RR C,D,E,A,B,8 |
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|
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RR A,B,C,D,E,10 |
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RR D,E,A,B,C,12 |
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RR B,C,D,E,A,14 |
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RR E,A,B,C,D,16 |
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RR C,D,E,A,B,18 |
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|
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%xdefine F F2 |
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|
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RR A,B,C,D,E,20 |
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RR D,E,A,B,C,22 |
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RR B,C,D,E,A,24 |
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RR E,A,B,C,D,26 |
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RR C,D,E,A,B,28 |
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|
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RR A,B,C,D,E,30 |
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RR D,E,A,B,C,32 |
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RR B,C,D,E,A,34 |
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RR E,A,B,C,D,36 |
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RR C,D,E,A,B,38 |
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|
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%xdefine F F3 |
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|
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RR A,B,C,D,E,40 |
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RR D,E,A,B,C,42 |
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RR B,C,D,E,A,44 |
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RR E,A,B,C,D,46 |
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RR C,D,E,A,B,48 |
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|
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RR A,B,C,D,E,50 |
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RR D,E,A,B,C,52 |
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RR B,C,D,E,A,54 |
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RR E,A,B,C,D,56 |
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RR C,D,E,A,B,58 |
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|
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%xdefine F F4 |
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|
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%if (%1 == 1) ;; if code loops through more than one block |
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add BUFFER_PTR, 64 ;; move to next 64-byte block |
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cmp BUFFER_PTR, BUFFER_END ;; check if current block is the last one |
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cmovae BUFFER_PTR, K_BASE ;; smart way to signal the last iteration |
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%else |
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%xdefine W_NO_TAIL_PRECALC 1 ;; no software pipelining for single block interface |
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%endif |
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|
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RR A,B,C,D,E,60 |
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RR D,E,A,B,C,62 |
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RR B,C,D,E,A,64 |
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RR E,A,B,C,D,66 |
||||
RR C,D,E,A,B,68 |
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|
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RR A,B,C,D,E,70 |
||||
RR D,E,A,B,C,72 |
||||
RR B,C,D,E,A,74 |
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RR E,A,B,C,D,76 |
||||
RR C,D,E,A,B,78 |
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|
||||
UPDATE_HASH [HASH_PTR ],A |
||||
UPDATE_HASH [HASH_PTR+ 4],B |
||||
UPDATE_HASH [HASH_PTR+ 8],C |
||||
UPDATE_HASH [HASH_PTR+12],D |
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UPDATE_HASH [HASH_PTR+16],E |
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|
||||
%if (%1 == 1) |
||||
jmp %%_loop |
||||
|
||||
align 32 |
||||
%%_end: |
||||
%endif |
||||
|
||||
|
||||
%xdefine W_NO_TAIL_PRECALC 0 |
||||
%xdefine F %error |
||||
|
||||
%endmacro |
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|
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|
||||
%macro F1 3 |
||||
mov T1,%2 |
||||
xor T1,%3 |
||||
and T1,%1 |
||||
xor T1,%3 |
||||
%endmacro |
||||
|
||||
%macro F2 3 |
||||
mov T1,%3 |
||||
xor T1,%2 |
||||
xor T1,%1 |
||||
%endmacro |
||||
|
||||
%macro F3 3 |
||||
mov T1,%2 |
||||
mov T2,%1 |
||||
or T1,%1 |
||||
and T2,%2 |
||||
and T1,%3 |
||||
or T1,T2 |
||||
%endmacro |
||||
|
||||
%define F4 F2 |
||||
|
||||
%macro UPDATE_HASH 2 |
||||
add %2, %1 |
||||
mov %1, %2 |
||||
%endmacro |
||||
|
||||
|
||||
%macro W_PRECALC 1 |
||||
%xdefine i (%1) |
||||
|
||||
%if (i < 20) |
||||
%xdefine K_XMM 0 |
||||
%elif (i < 40) |
||||
%xdefine K_XMM 16 |
||||
%elif (i < 60) |
||||
%xdefine K_XMM 32 |
||||
%else |
||||
%xdefine K_XMM 48 |
||||
%endif |
||||
|
||||
%if (i<16 || (i>=80 && i<(80 + W_PRECALC_AHEAD))) |
||||
|
||||
%if (W_NO_TAIL_PRECALC == 0) |
||||
|
||||
%xdefine i ((%1) % 80) ;; pre-compute for the next iteration |
||||
|
||||
%if (i == 0) |
||||
W_PRECALC_RESET |
||||
%endif |
||||
|
||||
|
||||
W_PRECALC_00_15 |
||||
%endif |
||||
|
||||
%elif (i < 32) |
||||
W_PRECALC_16_31 |
||||
%elif (i < 80) ;; rounds 32-79 |
||||
W_PRECALC_32_79 |
||||
%endif |
||||
%endmacro |
||||
|
||||
%macro W_PRECALC_RESET 0 |
||||
%xdefine W W0 |
||||
%xdefine W_minus_04 W4 |
||||
%xdefine W_minus_08 W8 |
||||
%xdefine W_minus_12 W12 |
||||
%xdefine W_minus_16 W16 |
||||
%xdefine W_minus_20 W20 |
||||
%xdefine W_minus_24 W24 |
||||
%xdefine W_minus_28 W28 |
||||
%xdefine W_minus_32 W |
||||
%endmacro |
||||
|
||||
%macro W_PRECALC_ROTATE 0 |
||||
%xdefine W_minus_32 W_minus_28 |
||||
%xdefine W_minus_28 W_minus_24 |
||||
%xdefine W_minus_24 W_minus_20 |
||||
%xdefine W_minus_20 W_minus_16 |
||||
%xdefine W_minus_16 W_minus_12 |
||||
%xdefine W_minus_12 W_minus_08 |
||||
%xdefine W_minus_08 W_minus_04 |
||||
%xdefine W_minus_04 W |
||||
%xdefine W W_minus_32 |
||||
%endmacro |
||||
|
||||
%xdefine W_PRECALC_AHEAD 16 |
||||
%xdefine W_NO_TAIL_PRECALC 0 |
||||
|
||||
|
||||
%xdefine xmm_mov movdqa |
||||
|
||||
%macro W_PRECALC_00_15 0 |
||||
;; message scheduling pre-compute for rounds 0-15 |
||||
%if ((i & 3) == 0) ;; blended SSE and ALU instruction scheduling, 1 vector iteration per 4 rounds |
||||
movdqu W_TMP, [BUFFER_PTR + (i * 4)] |
||||
%elif ((i & 3) == 1) |
||||
pshufb W_TMP, XMM_SHUFB_BSWAP |
||||
movdqa W, W_TMP |
||||
%elif ((i & 3) == 2) |
||||
paddd W_TMP, [K_BASE] |
||||
%elif ((i & 3) == 3) |
||||
movdqa [WK(i&~3)], W_TMP |
||||
|
||||
W_PRECALC_ROTATE |
||||
%endif |
||||
%endmacro |
||||
|
||||
%macro W_PRECALC_16_31 0 |
||||
;; message scheduling pre-compute for rounds 16-31 |
||||
;; calculating last 32 w[i] values in 8 XMM registers |
||||
;; pre-calculate K+w[i] values and store to mem, for later load by ALU add instruction |
||||
;; |
||||
;; "brute force" vectorization for rounds 16-31 only due to w[i]->w[i-3] dependency |
||||
;; |
||||
%if ((i & 3) == 0) ;; blended SSE and ALU instruction scheduling, 1 vector iteration per 4 rounds |
||||
movdqa W, W_minus_12 |
||||
palignr W, W_minus_16, 8 ;; w[i-14] |
||||
movdqa W_TMP, W_minus_04 |
||||
psrldq W_TMP, 4 ;; w[i-3] |
||||
pxor W, W_minus_08 |
||||
%elif ((i & 3) == 1) |
||||
pxor W_TMP, W_minus_16 |
||||
pxor W, W_TMP |
||||
movdqa W_TMP2, W |
||||
movdqa W_TMP, W |
||||
pslldq W_TMP2, 12 |
||||
%elif ((i & 3) == 2) |
||||
psrld W, 31 |
||||
pslld W_TMP, 1 |
||||
por W_TMP, W |
||||
movdqa W, W_TMP2 |
||||
psrld W_TMP2, 30 |
||||
pslld W, 2 |
||||
%elif ((i & 3) == 3) |
||||
pxor W_TMP, W |
||||
pxor W_TMP, W_TMP2 |
||||
movdqa W, W_TMP |
||||
paddd W_TMP, [K_BASE + K_XMM] |
||||
movdqa [WK(i&~3)],W_TMP |
||||
|
||||
W_PRECALC_ROTATE |
||||
%endif |
||||
%endmacro |
||||
|
||||
%macro W_PRECALC_32_79 0 |
||||
;; in SHA-1 specification: w[i] = (w[i-3] ^ w[i-8] ^ w[i-14] ^ w[i-16]) rol 1 |
||||
;; instead we do equal: w[i] = (w[i-6] ^ w[i-16] ^ w[i-28] ^ w[i-32]) rol 2 |
||||
;; allows more efficient vectorization since w[i]=>w[i-3] dependency is broken |
||||
;; |
||||
%if ((i & 3) == 0) ;; blended SSE and ALU instruction scheduling, 1 vector iteration per 4 rounds |
||||
movdqa W_TMP, W_minus_04 |
||||
pxor W, W_minus_28 ;; W is W_minus_32 before xor |
||||
palignr W_TMP, W_minus_08, 8 |
||||
%elif ((i & 3) == 1) |
||||
pxor W, W_minus_16 |
||||
pxor W, W_TMP |
||||
movdqa W_TMP, W |
||||
%elif ((i & 3) == 2) |
||||
psrld W, 30 |
||||
pslld W_TMP, 2 |
||||
por W_TMP, W |
||||
%elif ((i & 3) == 3) |
||||
movdqa W, W_TMP |
||||
paddd W_TMP, [K_BASE + K_XMM] |
||||
movdqa [WK(i&~3)],W_TMP |
||||
|
||||
W_PRECALC_ROTATE |
||||
%endif |
||||
%endmacro |
||||
|
||||
%macro RR 6 ;; RR does two rounds of SHA-1 back to back with W pre-calculation |
||||
|
||||
;; TEMP = A |
||||
;; A = F( i, B, C, D ) + E + ROTATE_LEFT( A, 5 ) + W[i] + K(i) |
||||
;; C = ROTATE_LEFT( B, 30 ) |
||||
;; D = C |
||||
;; E = D |
||||
;; B = TEMP |
||||
|
||||
W_PRECALC (%6 + W_PRECALC_AHEAD) |
||||
F %2, %3, %4 ;; F returns result in T1 |
||||
add %5, [WK(%6)] |
||||
rol %2, 30 |
||||
mov T2, %1 |
||||
add %4, [WK(%6 + 1)] |
||||
rol T2, 5 |
||||
add %5, T1 |
||||
|
||||
W_PRECALC (%6 + W_PRECALC_AHEAD + 1) |
||||
add T2, %5 |
||||
mov %5, T2 |
||||
rol T2, 5 |
||||
add %4, T2 |
||||
F %1, %2, %3 ;; F returns result in T1 |
||||
add %4, T1 |
||||
rol %1, 30 |
||||
|
||||
;; write: %1, %2 |
||||
;; rotate: %1<=%4, %2<=%5, %3<=%1, %4<=%2, %5<=%3 |
||||
%endmacro |
||||
|
||||
|
||||
|
||||
;;---------------------- |
||||
section .data align=128 |
||||
|
||||
%xdefine K1 0x5a827999 |
||||
%xdefine K2 0x6ed9eba1 |
||||
%xdefine K3 0x8f1bbcdc |
||||
%xdefine K4 0xca62c1d6 |
||||
|
||||
align 128 |
||||
K_XMM_AR: |
||||
DD K1, K1, K1, K1 |
||||
DD K2, K2, K2, K2 |
||||
DD K3, K3, K3, K3 |
||||
DD K4, K4, K4, K4 |
||||
|
||||
align 16 |
||||
bswap_shufb_ctl: |
||||
DD 00010203h |
||||
DD 04050607h |
||||
DD 08090a0bh |
||||
DD 0c0d0e0fh |
||||
|
||||
;; dispatch pointer, points to the init routine for the first invocation |
||||
sha1_update_intel_dispatched: |
||||
DQ sha1_update_intel_init_ |
||||
|
||||
;;---------------------- |
||||
section .text align=4096 |
||||
|
||||
SHA1_VECTOR_ASM sha1_update_intel_ssse3_, multiblock |
||||
|
||||
align 32 |
||||
sha1_update_intel_init_: ;; we get here with the first time invocation |
||||
call sha1_update_intel_dispacth_init_ |
||||
INTEL_SHA1_UPDATE_FUNCNAME: ;; we get here after init |
||||
jmp qword [sha1_update_intel_dispatched] |
||||
|
||||
;; CPUID feature flag based dispatch |
||||
sha1_update_intel_dispacth_init_: |
||||
push rax |
||||
push rbx |
||||
push rcx |
||||
push rdx |
||||
push rsi |
||||
|
||||
lea rsi, [INTEL_SHA1_UPDATE_DEFAULT_DISPATCH] |
||||
|
||||
mov eax, 1 |
||||
cpuid |
||||
|
||||
test ecx, 0200h ;; SSSE3 support, CPUID.1.ECX[bit 9] |
||||
jz _done |
||||
|
||||
lea rsi, [sha1_update_intel_ssse3_] |
||||
|
||||
_done: |
||||
mov [sha1_update_intel_dispatched], rsi |
||||
|
||||
pop rsi |
||||
pop rdx |
||||
pop rcx |
||||
pop rbx |
||||
pop rax |
||||
ret |
||||
|
||||
;;---------------------- |
||||
;; in the case a default SHA-1 update function implementation was not provided |
||||
;; and code was invoked on a non-SSSE3 supporting CPU, dispatch handles this |
||||
;; failure in a safest way - jumps to the stub function with UD2 instruction below |
||||
sha1_intel_non_ssse3_cpu_stub_: |
||||
ud2 ;; in the case no default SHA-1 was provided non-SSSE3 CPUs safely fail here |
||||
ret |
||||
|
||||
; END |
||||
;---------------------- |
||||
@ -0,0 +1,5 @@ |
||||
// !build amd64
|
||||
|
||||
package sha1 |
||||
|
||||
//go:generate yasm -f macho64 sha1_sse3_amd64.asm -o sha1_sse3_amd64.syso
|
||||
@ -0,0 +1,5 @@ |
||||
// !build amd64
|
||||
|
||||
package sha1 |
||||
|
||||
//go:generate yasm -f elf64 sha1_sse3_amd64.asm -o sha1_sse3_amd64.syso
|
||||
@ -0,0 +1,5 @@ |
||||
// !build amd64
|
||||
|
||||
package sha1 |
||||
|
||||
//go:generate yasm -f win64 -DWIN_ABI=1 sha1_sse3_amd64.asm -o sha1_sse3_amd64.syso
|
||||
@ -0,0 +1,202 @@ |
||||
|
||||
Apache License |
||||
Version 2.0, January 2004 |
||||
http://www.apache.org/licenses/ |
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION |
||||
|
||||
1. Definitions. |
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction, |
||||
and distribution as defined by Sections 1 through 9 of this document. |
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by |
||||
the copyright owner that is granting the License. |
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all |
||||
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||||
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||||
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||||
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||||
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"You" (or "Your") shall mean an individual or Legal Entity |
||||
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||||
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TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION |
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