Merge pull request #98 from harshavardhana/pr_out_add_sha1_avx2_supported_fast_implementation_with_some_crc32c_cleanup
Harshavardhana
10 years ago
commit
3fe2c2af01
@ -0,0 +1,40 @@ |
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/* |
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* Mini Object Storage, (C) 2014 Minio, Inc. |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); |
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* you may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0
|
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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|
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// +build amd64
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package crc32c |
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// #include <stdint.h>
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// uint32_t crc32c_pcl(uint8_t *buf, int32_t len, uint32_t prev_crc);
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import "C" |
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import ( |
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"errors" |
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"unsafe" |
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) |
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func Crc32c(buffer []byte) (uint32, error) { |
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var length = len(buffer) |
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if length == 0 { |
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return 0, errors.New("Invalid input") |
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} |
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var cbuf *C.uint8_t |
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cbuf = (*C.uint8_t)(unsafe.Pointer(&buffer[0])) |
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crc := C.crc32c_pcl(cbuf, C.int32_t(length), C.uint32_t(0)) |
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return uint32(crc), nil |
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} |
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@ -0,0 +1,24 @@ |
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package crc32c |
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import ( |
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. "gopkg.in/check.v1" |
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"testing" |
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) |
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func Test(t *testing.T) { TestingT(t) } |
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type MySuite struct{} |
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var _ = Suite(&MySuite{}) |
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func (s *MySuite) TestCrc32c(c *C) { |
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data_1 := []byte("Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset sheets containing Lorem Ipsum passages, and more recently with desktop publishing software like Aldus PageMaker including versions of Lorem Ipsum.") |
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crc, err := Crc32c(data_1) |
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c.Assert(err, IsNil) |
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data_2 := []byte("Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset sheets containing Lorem Ipsum passages, and more recently with desktop publishing software like Aldus PageMaker including versions of Lorem Ipsum.") |
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newcrc, newerr := Crc32c(data_2) |
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c.Assert(newerr, IsNil) |
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c.Assert(crc, Equals, newcrc) |
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} |
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@ -0,0 +1,71 @@ |
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/* |
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* Mini Object Storage, (C) 2014 Minio, Inc. |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); |
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* you may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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// +build amd64
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package sha1 |
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// #include <stdio.h>
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// #include <stdint.h>
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// void sha1_transform(int32_t *hash, const char* input, size_t num_blocks);
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import "C" |
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import ( |
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"errors" |
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"github.com/minio-io/minio/pkgs/cpu" |
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"unsafe" |
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) |
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const ( |
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SHA1_BLOCKSIZE = 64 |
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SHA1_DIGESTSIZE = 20 |
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) |
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func Sha1(buffer []byte) ([]int32, error) { |
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if !cpu.HasAVX2() { |
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// Unsupported processor but do not error out tests
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return []int32{0}, nil |
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} |
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var shbuf []int32 |
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var cbuffer *C.char |
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shbuf = make([]int32, SHA1_DIGESTSIZE) |
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var length = len(buffer) |
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if length == 0 { |
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return []int32{0}, errors.New("Invalid input") |
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} |
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rem := length % SHA1_BLOCKSIZE |
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padded_len := length |
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if rem > 0 { |
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padded_len = length + (SHA1_BLOCKSIZE - rem) |
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} |
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rounds := padded_len / SHA1_BLOCKSIZE |
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pad := padded_len - length |
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if pad > 0 { |
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s := make([]byte, pad) |
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// Expand with new padded blocks to the byte array
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buffer = append(buffer, s...) |
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} |
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cshbuf := (*C.int32_t)(unsafe.Pointer(&shbuf[0])) |
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cbuffer = (*C.char)(unsafe.Pointer(&buffer[0])) |
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C.sha1_transform(cshbuf, cbuffer, C.size_t(rounds)) |
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return shbuf, nil |
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} |
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@ -0,0 +1,971 @@ |
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/* |
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* Implement fast SHA-1 with AVX2 instructions. (x86_64) |
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* |
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* This file is provided under a dual BSD/GPLv2 license. When using or |
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* redistributing this file, you may do so under either license. |
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* |
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* GPL LICENSE SUMMARY |
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* |
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* Copyright(c) 2014 Intel Corporation. |
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* |
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License for more details. |
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* |
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* Contact Information: |
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* Ilya Albrekht <ilya.albrekht@intel.com>
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* Maxim Locktyukhin <maxim.locktyukhin@intel.com>
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* Ronen Zohar <ronen.zohar@intel.com>
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* Chandramouli Narayanan <mouli@linux.intel.com>
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* |
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* BSD LICENSE |
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* |
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* Copyright(c) 2014 Intel Corporation. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* Neither the name of Intel Corporation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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*/ |
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/* |
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* SHA-1 implementation with Intel(R) AVX2 instruction set extensions. |
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* |
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*This implementation is based on the previous SSSE3 release: |
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*Visit http://software.intel.com/en-us/articles/ |
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*and refer to improving-the-performance-of-the-secure-hash-algorithm-1/ |
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* |
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*Updates 20-byte SHA-1 record in 'hash' for even number of |
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*'num_blocks' consecutive 64-byte blocks |
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* |
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*/ |
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#ifndef ASM_NL |
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#define ASM_NL ;
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#endif |
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#ifndef __ALIGN |
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#define __ALIGN .align 4,0x90 |
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#endif |
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#define ALIGN __ALIGN |
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#ifndef ENTRY |
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#define ENTRY(name) \ |
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.globl name ASM_NL \ |
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ALIGN ASM_NL \ |
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name: |
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#endif |
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#ifndef END |
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#define END(name) \ |
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.size name, .-name |
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#endif |
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#ifndef ENDPROC |
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#define ENDPROC(name) \ |
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.type name, @function ASM_NL \
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END(name) |
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#endif |
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#define NUM_INVALID 100 |
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#define TYPE_R32 0 |
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#define TYPE_R64 1 |
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#define TYPE_XMM 2 |
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#define TYPE_INVALID 100 |
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.macro R32_NUM opd r32 |
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\opd = NUM_INVALID |
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.ifc \r32,%eax |
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\opd = 0 |
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.endif |
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.ifc \r32,%ecx |
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\opd = 1 |
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.endif |
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.ifc \r32,%edx |
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\opd = 2 |
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.endif |
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.ifc \r32,%ebx |
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\opd = 3 |
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.endif |
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.ifc \r32,%esp |
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\opd = 4 |
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.endif |
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.ifc \r32,%ebp |
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\opd = 5 |
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.endif |
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.ifc \r32,%esi |
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\opd = 6 |
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.endif |
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.ifc \r32,%edi |
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\opd = 7 |
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.endif |
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#ifdef X86_64 |
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.ifc \r32,%r8d |
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\opd = 8 |
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.endif |
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.ifc \r32,%r9d |
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\opd = 9 |
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.endif |
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.ifc \r32,%r10d |
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\opd = 10 |
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.endif |
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.ifc \r32,%r11d |
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\opd = 11 |
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.endif |
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.ifc \r32,%r12d |
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\opd = 12 |
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.endif |
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.ifc \r32,%r13d |
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\opd = 13 |
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.endif |
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.ifc \r32,%r14d |
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\opd = 14 |
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.endif |
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.ifc \r32,%r15d |
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\opd = 15 |
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.endif |
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#endif |
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.endm |
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|
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.macro R64_NUM opd r64 |
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\opd = NUM_INVALID |
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#ifdef X86_64 |
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.ifc \r64,%rax |
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\opd = 0 |
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.endif |
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.ifc \r64,%rcx |
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\opd = 1 |
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.endif |
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.ifc \r64,%rdx |
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\opd = 2 |
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.endif |
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.ifc \r64,%rbx |
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\opd = 3 |
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.endif |
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.ifc \r64,%rsp |
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\opd = 4 |
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.endif |
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.ifc \r64,%rbp |
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\opd = 5 |
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.endif |
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.ifc \r64,%rsi |
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\opd = 6 |
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.endif |
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.ifc \r64,%rdi |
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\opd = 7 |
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.endif |
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.ifc \r64,%r8 |
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\opd = 8 |
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.endif |
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.ifc \r64,%r9 |
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\opd = 9 |
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.endif |
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.ifc \r64,%r10 |
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\opd = 10 |
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.endif |
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.ifc \r64,%r11 |
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\opd = 11 |
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.endif |
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.ifc \r64,%r12 |
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\opd = 12 |
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.endif |
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.ifc \r64,%r13 |
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\opd = 13 |
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.endif |
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.ifc \r64,%r14 |
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\opd = 14 |
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.endif |
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.ifc \r64,%r15 |
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\opd = 15 |
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.endif |
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#endif |
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.endm |
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|
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.macro XMM_NUM opd xmm |
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\opd = NUM_INVALID |
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.ifc \xmm,%xmm0 |
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\opd = 0 |
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.endif |
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.ifc \xmm,%xmm1 |
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\opd = 1 |
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.endif |
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.ifc \xmm,%xmm2 |
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\opd = 2 |
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.endif |
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.ifc \xmm,%xmm3 |
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\opd = 3 |
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.endif |
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.ifc \xmm,%xmm4 |
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\opd = 4 |
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.endif |
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.ifc \xmm,%xmm5 |
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\opd = 5 |
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.endif |
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.ifc \xmm,%xmm6 |
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\opd = 6 |
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.endif |
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.ifc \xmm,%xmm7 |
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\opd = 7 |
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.endif |
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.ifc \xmm,%xmm8 |
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\opd = 8 |
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.endif |
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.ifc \xmm,%xmm9 |
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\opd = 9 |
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.endif |
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.ifc \xmm,%xmm10 |
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\opd = 10 |
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.endif |
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.ifc \xmm,%xmm11 |
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\opd = 11 |
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.endif |
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.ifc \xmm,%xmm12 |
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\opd = 12 |
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.endif |
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.ifc \xmm,%xmm13 |
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\opd = 13 |
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.endif |
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.ifc \xmm,%xmm14 |
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\opd = 14 |
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.endif |
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.ifc \xmm,%xmm15 |
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\opd = 15 |
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.endif |
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.endm |
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|
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.macro TYPE type reg |
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R32_NUM reg_type_r32 \reg |
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R64_NUM reg_type_r64 \reg |
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XMM_NUM reg_type_xmm \reg |
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.if reg_type_r64 <> NUM_INVALID |
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\type = TYPE_R64 |
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.elseif reg_type_r32 <> NUM_INVALID |
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\type = TYPE_R32 |
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.elseif reg_type_xmm <> NUM_INVALID |
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\type = TYPE_XMM |
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.else |
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\type = TYPE_INVALID |
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.endif |
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.endm |
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|
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.macro PFX_OPD_SIZE
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.byte 0x66
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.endm |
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.macro PFX_REX opd1 opd2 W=0 |
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.if ((\opd1 | \opd2) & 8) || \W |
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.byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) | (\W << 3) |
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.endif |
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.endm |
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|
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.macro MODRM mod opd1 opd2 |
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.byte \mod | (\opd1 & 7) | ((\opd2 & 7) << 3) |
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.endm |
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|
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.macro PSHUFB_XMM xmm1 xmm2 |
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XMM_NUM pshufb_opd1 \xmm1 |
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XMM_NUM pshufb_opd2 \xmm2 |
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PFX_OPD_SIZE |
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PFX_REX pshufb_opd1 pshufb_opd2 |
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.byte 0x0f, 0x38, 0x00 |
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MODRM 0xc0 pshufb_opd1 pshufb_opd2 |
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.endm |
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|
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.macro PCLMULQDQ imm8 xmm1 xmm2 |
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XMM_NUM clmul_opd1 \xmm1 |
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XMM_NUM clmul_opd2 \xmm2 |
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PFX_OPD_SIZE |
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PFX_REX clmul_opd1 clmul_opd2 |
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.byte 0x0f, 0x3a, 0x44 |
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MODRM 0xc0 clmul_opd1 clmul_opd2 |
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.byte \imm8 |
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.endm |
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|
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.macro PEXTRD imm8 xmm gpr |
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R32_NUM extrd_opd1 \gpr |
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XMM_NUM extrd_opd2 \xmm |
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PFX_OPD_SIZE |
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PFX_REX extrd_opd1 extrd_opd2 |
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.byte 0x0f, 0x3a, 0x16 |
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MODRM 0xc0 extrd_opd1 extrd_opd2 |
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.byte \imm8 |
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.endm |
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|
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.macro MOVQ_R64_XMM opd1 opd2 |
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TYPE movq_r64_xmm_opd1_type \opd1 |
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.if movq_r64_xmm_opd1_type == TYPE_XMM |
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XMM_NUM movq_r64_xmm_opd1 \opd1 |
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R64_NUM movq_r64_xmm_opd2 \opd2 |
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.else |
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R64_NUM movq_r64_xmm_opd1 \opd1 |
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XMM_NUM movq_r64_xmm_opd2 \opd2 |
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.endif |
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PFX_OPD_SIZE |
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PFX_REX movq_r64_xmm_opd1 movq_r64_xmm_opd2 1 |
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.if movq_r64_xmm_opd1_type == TYPE_XMM |
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.byte 0x0f, 0x7e |
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.else |
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.byte 0x0f, 0x6e |
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.endif |
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MODRM 0xc0 movq_r64_xmm_opd1 movq_r64_xmm_opd2 |
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.endm |
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|
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#define CTX %rdi /* arg1 */ |
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#define BUF %rsi /* arg2 */ |
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#define CNT %rdx /* arg3 */ |
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|
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#define REG_A %ecx |
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#define REG_B %esi |
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#define REG_C %edi |
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#define REG_D %eax |
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#define REG_E %edx |
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#define REG_TB %ebx |
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#define REG_TA %r12d |
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#define REG_RA %rcx |
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#define REG_RB %rsi |
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#define REG_RC %rdi |
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#define REG_RD %rax |
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#define REG_RE %rdx |
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#define REG_RTA %r12 |
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#define REG_RTB %rbx |
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#define REG_T1 %ebp |
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#define xmm_mov vmovups |
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#define avx2_zeroupper vzeroupper |
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#define RND_F1 1 |
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#define RND_F2 2 |
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#define RND_F3 3 |
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|
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.macro REGALLOC
|
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.set A, REG_A |
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.set B, REG_B |
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.set C, REG_C |
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.set D, REG_D |
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.set E, REG_E |
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.set TB, REG_TB |
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.set TA, REG_TA |
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|
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.set RA, REG_RA |
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.set RB, REG_RB |
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.set RC, REG_RC |
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.set RD, REG_RD |
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.set RE, REG_RE |
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|
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.set RTA, REG_RTA |
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.set RTB, REG_RTB |
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|
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.set T1, REG_T1 |
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.endm |
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|
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#define K_BASE %r8 |
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#define HASH_PTR %r9 |
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#define BUFFER_PTR %r10 |
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#define BUFFER_PTR2 %r13 |
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#define BUFFER_END %r11 |
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|
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#define PRECALC_BUF %r14 |
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#define WK_BUF %r15 |
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|
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#define W_TMP %xmm0 |
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#define WY_TMP %ymm0 |
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#define WY_TMP2 %ymm9 |
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|
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# AVX2 variables |
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#define WY0 %ymm3 |
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#define WY4 %ymm5 |
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#define WY08 %ymm7 |
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#define WY12 %ymm8 |
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#define WY16 %ymm12 |
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#define WY20 %ymm13 |
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#define WY24 %ymm14 |
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#define WY28 %ymm15 |
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|
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#define YMM_SHUFB_BSWAP %ymm10 |
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|
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/* |
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* Keep 2 iterations precalculated at a time: |
||||
* - 80 DWORDs per iteration * 2 |
||||
*/ |
||||
#define W_SIZE (80*2*2 +16) |
||||
|
||||
#define WK(t) ((((t) % 80) / 4)*32 + ( (t) % 4)*4 + ((t)/80)*16 )(WK_BUF) |
||||
#define PRECALC_WK(t) ((t)*2*2)(PRECALC_BUF) |
||||
|
||||
|
||||
.macro UPDATE_HASH hash, val |
||||
add \hash, \val |
||||
mov \val, \hash |
||||
.endm |
||||
|
||||
.macro PRECALC_RESET_WY
|
||||
.set WY_00, WY0 |
||||
.set WY_04, WY4 |
||||
.set WY_08, WY08 |
||||
.set WY_12, WY12 |
||||
.set WY_16, WY16 |
||||
.set WY_20, WY20 |
||||
.set WY_24, WY24 |
||||
.set WY_28, WY28 |
||||
.set WY_32, WY_00 |
||||
.endm |
||||
|
||||
.macro PRECALC_ROTATE_WY
|
||||
/* Rotate macros */ |
||||
.set WY_32, WY_28 |
||||
.set WY_28, WY_24 |
||||
.set WY_24, WY_20 |
||||
.set WY_20, WY_16 |
||||
.set WY_16, WY_12 |
||||
.set WY_12, WY_08 |
||||
.set WY_08, WY_04 |
||||
.set WY_04, WY_00 |
||||
.set WY_00, WY_32 |
||||
|
||||
/* Define register aliases */ |
||||
.set WY, WY_00 |
||||
.set WY_minus_04, WY_04 |
||||
.set WY_minus_08, WY_08 |
||||
.set WY_minus_12, WY_12 |
||||
.set WY_minus_16, WY_16 |
||||
.set WY_minus_20, WY_20 |
||||
.set WY_minus_24, WY_24 |
||||
.set WY_minus_28, WY_28 |
||||
.set WY_minus_32, WY |
||||
.endm |
||||
|
||||
.macro PRECALC_00_15
|
||||
.if (i == 0) # Initialize and rotate registers |
||||
PRECALC_RESET_WY |
||||
PRECALC_ROTATE_WY |
||||
.endif |
||||
|
||||
/* message scheduling pre-compute for rounds 0-15 */ |
||||
.if ((i & 7) == 0) |
||||
/* |
||||
* blended AVX2 and ALU instruction scheduling |
||||
* 1 vector iteration per 8 rounds |
||||
*/ |
||||
vmovdqu ((i * 2) + PRECALC_OFFSET)(BUFFER_PTR), W_TMP |
||||
.elseif ((i & 7) == 1) |
||||
vinsertf128 $1, (((i-1) * 2)+PRECALC_OFFSET)(BUFFER_PTR2),\ |
||||
WY_TMP, WY_TMP |
||||
.elseif ((i & 7) == 2) |
||||
vpshufb YMM_SHUFB_BSWAP, WY_TMP, WY |
||||
.elseif ((i & 7) == 4) |
||||
vpaddd K_XMM(K_BASE), WY, WY_TMP |
||||
.elseif ((i & 7) == 7) |
||||
vmovdqu WY_TMP, PRECALC_WK(i&~7) |
||||
|
||||
PRECALC_ROTATE_WY |
||||
.endif |
||||
.endm |
||||
|
||||
.macro PRECALC_16_31
|
||||
/* |
||||
* message scheduling pre-compute for rounds 16-31 |
||||
* calculating last 32 w[i] values in 8 XMM registers |
||||
* pre-calculate K+w[i] values and store to mem |
||||
* for later load by ALU add instruction |
||||
* |
||||
* "brute force" vectorization for rounds 16-31 only |
||||
* due to w[i]->w[i-3] dependency |
||||
*/ |
||||
.if ((i & 7) == 0) |
||||
/* |
||||
* blended AVX2 and ALU instruction scheduling |
||||
* 1 vector iteration per 8 rounds |
||||
*/ |
||||
/* w[i-14] */ |
||||
vpalignr $8, WY_minus_16, WY_minus_12, WY |
||||
vpsrldq $4, WY_minus_04, WY_TMP /* w[i-3] */ |
||||
.elseif ((i & 7) == 1) |
||||
vpxor WY_minus_08, WY, WY |
||||
vpxor WY_minus_16, WY_TMP, WY_TMP |
||||
.elseif ((i & 7) == 2) |
||||
vpxor WY_TMP, WY, WY |
||||
vpslldq $12, WY, WY_TMP2 |
||||
.elseif ((i & 7) == 3) |
||||
vpslld $1, WY, WY_TMP |
||||
vpsrld $31, WY, WY |
||||
.elseif ((i & 7) == 4) |
||||
vpor WY, WY_TMP, WY_TMP |
||||
vpslld $2, WY_TMP2, WY |
||||
.elseif ((i & 7) == 5) |
||||
vpsrld $30, WY_TMP2, WY_TMP2 |
||||
vpxor WY, WY_TMP, WY_TMP |
||||
.elseif ((i & 7) == 7) |
||||
vpxor WY_TMP2, WY_TMP, WY |
||||
vpaddd K_XMM(K_BASE), WY, WY_TMP |
||||
vmovdqu WY_TMP, PRECALC_WK(i&~7) |
||||
|
||||
PRECALC_ROTATE_WY |
||||
.endif |
||||
.endm |
||||
|
||||
.macro PRECALC_32_79
|
||||
/* |
||||
* in SHA-1 specification: |
||||
* w[i] = (w[i-3] ^ w[i-8] ^ w[i-14] ^ w[i-16]) rol 1 |
||||
* instead we do equal: |
||||
* w[i] = (w[i-6] ^ w[i-16] ^ w[i-28] ^ w[i-32]) rol 2 |
||||
* allows more efficient vectorization |
||||
* since w[i]=>w[i-3] dependency is broken |
||||
*/ |
||||
|
||||
.if ((i & 7) == 0) |
||||
/* |
||||
* blended AVX2 and ALU instruction scheduling |
||||
* 1 vector iteration per 8 rounds |
||||
*/ |
||||
vpalignr $8, WY_minus_08, WY_minus_04, WY_TMP |
||||
.elseif ((i & 7) == 1) |
||||
/* W is W_minus_32 before xor */ |
||||
vpxor WY_minus_28, WY, WY |
||||
.elseif ((i & 7) == 2) |
||||
vpxor WY_minus_16, WY_TMP, WY_TMP |
||||
.elseif ((i & 7) == 3) |
||||
vpxor WY_TMP, WY, WY |
||||
.elseif ((i & 7) == 4) |
||||
vpslld $2, WY, WY_TMP |
||||
.elseif ((i & 7) == 5) |
||||
vpsrld $30, WY, WY |
||||
vpor WY, WY_TMP, WY |
||||
.elseif ((i & 7) == 7) |
||||
vpaddd K_XMM(K_BASE), WY, WY_TMP |
||||
vmovdqu WY_TMP, PRECALC_WK(i&~7) |
||||
|
||||
PRECALC_ROTATE_WY |
||||
.endif |
||||
.endm |
||||
|
||||
.macro PRECALC r, s |
||||
.set i, \r |
||||
|
||||
.if (i < 40) |
||||
.set K_XMM, 32*0 |
||||
.elseif (i < 80) |
||||
.set K_XMM, 32*1 |
||||
.elseif (i < 120) |
||||
.set K_XMM, 32*2 |
||||
.else |
||||
.set K_XMM, 32*3 |
||||
.endif |
||||
|
||||
.if (i<32) |
||||
PRECALC_00_15 \s |
||||
.elseif (i<64) |
||||
PRECALC_16_31 \s |
||||
.elseif (i < 160) |
||||
PRECALC_32_79 \s |
||||
.endif |
||||
.endm |
||||
|
||||
.macro ROTATE_STATE
|
||||
.set T_REG, E |
||||
.set E, D |
||||
.set D, C |
||||
.set C, B |
||||
.set B, TB |
||||
.set TB, A |
||||
.set A, T_REG |
||||
|
||||
.set T_REG, RE |
||||
.set RE, RD |
||||
.set RD, RC |
||||
.set RC, RB |
||||
.set RB, RTB |
||||
.set RTB, RA |
||||
.set RA, T_REG |
||||
.endm |
||||
|
||||
/* Macro relies on saved ROUND_Fx */ |
||||
|
||||
.macro RND_FUN f, r |
||||
.if (\f == RND_F1) |
||||
ROUND_F1 \r |
||||
.elseif (\f == RND_F2) |
||||
ROUND_F2 \r |
||||
.elseif (\f == RND_F3) |
||||
ROUND_F3 \r |
||||
.endif |
||||
.endm |
||||
|
||||
.macro RR r |
||||
.set round_id, (\r % 80) |
||||
|
||||
.if (round_id == 0) /* Precalculate F for first round */ |
||||
.set ROUND_FUNC, RND_F1 |
||||
mov B, TB |
||||
|
||||
rorx $(32-30), B, B /* b>>>2 */ |
||||
andn D, TB, T1 |
||||
and C, TB |
||||
xor T1, TB |
||||
.endif |
||||
|
||||
RND_FUN ROUND_FUNC, \r |
||||
ROTATE_STATE |
||||
|
||||
.if (round_id == 18) |
||||
.set ROUND_FUNC, RND_F2 |
||||
.elseif (round_id == 38) |
||||
.set ROUND_FUNC, RND_F3 |
||||
.elseif (round_id == 58) |
||||
.set ROUND_FUNC, RND_F2 |
||||
.endif |
||||
|
||||
.set round_id, ( (\r+1) % 80) |
||||
|
||||
RND_FUN ROUND_FUNC, (\r+1) |
||||
ROTATE_STATE |
||||
.endm |
||||
|
||||
.macro ROUND_F1 r |
||||
add WK(\r), E |
||||
|
||||
andn C, A, T1 /* ~b&d */ |
||||
lea (RE,RTB), E /* Add F from the previous round */ |
||||
|
||||
rorx $(32-5), A, TA /* T2 = A >>> 5 */ |
||||
rorx $(32-30),A, TB /* b>>>2 for next round */ |
||||
|
||||
PRECALC (\r) /* msg scheduling for next 2 blocks */ |
||||
|
||||
/* |
||||
* Calculate F for the next round |
||||
* (b & c) ^ andn[b, d] |
||||
*/ |
||||
and B, A /* b&c */ |
||||
xor T1, A /* F1 = (b&c) ^ (~b&d) */ |
||||
|
||||
lea (RE,RTA), E /* E += A >>> 5 */ |
||||
.endm |
||||
|
||||
.macro ROUND_F2 r |
||||
add WK(\r), E |
||||
lea (RE,RTB), E /* Add F from the previous round */ |
||||
|
||||
/* Calculate F for the next round */ |
||||
rorx $(32-5), A, TA /* T2 = A >>> 5 */ |
||||
.if ((round_id) < 79) |
||||
rorx $(32-30), A, TB /* b>>>2 for next round */ |
||||
.endif |
||||
PRECALC (\r) /* msg scheduling for next 2 blocks */ |
||||
|
||||
.if ((round_id) < 79) |
||||
xor B, A |
||||
.endif |
||||
|
||||
add TA, E /* E += A >>> 5 */ |
||||
|
||||
.if ((round_id) < 79) |
||||
xor C, A |
||||
.endif |
||||
.endm |
||||
|
||||
.macro ROUND_F3 r |
||||
add WK(\r), E |
||||
PRECALC (\r) /* msg scheduling for next 2 blocks */ |
||||
|
||||
lea (RE,RTB), E /* Add F from the previous round */ |
||||
|
||||
mov B, T1 |
||||
or A, T1 |
||||
|
||||
rorx $(32-5), A, TA /* T2 = A >>> 5 */ |
||||
rorx $(32-30), A, TB /* b>>>2 for next round */ |
||||
|
||||
/* Calculate F for the next round |
||||
* (b and c) or (d and (b or c)) |
||||
*/ |
||||
and C, T1 |
||||
and B, A |
||||
or T1, A |
||||
|
||||
add TA, E /* E += A >>> 5 */ |
||||
|
||||
.endm |
||||
|
||||
/* |
||||
* macro implements 80 rounds of SHA-1, for multiple blocks with s/w pipelining |
||||
*/ |
||||
.macro SHA1_PIPELINED_MAIN_BODY
|
||||
|
||||
REGALLOC |
||||
|
||||
mov (HASH_PTR), A |
||||
mov 4(HASH_PTR), B |
||||
mov 8(HASH_PTR), C |
||||
mov 12(HASH_PTR), D |
||||
mov 16(HASH_PTR), E |
||||
|
||||
mov %rsp, PRECALC_BUF |
||||
lea (2*4*80+32)(%rsp), WK_BUF |
||||
|
||||
# Precalc WK for first 2 blocks |
||||
PRECALC_OFFSET = 0 |
||||
.set i, 0 |
||||
.rept 160
|
||||
PRECALC i |
||||
.set i, i + 1 |
||||
.endr |
||||
PRECALC_OFFSET = 128 |
||||
xchg WK_BUF, PRECALC_BUF |
||||
|
||||
.align 32
|
||||
_loop: |
||||
/* |
||||
* code loops through more than one block |
||||
* we use K_BASE value as a signal of a last block, |
||||
* it is set below by: cmovae BUFFER_PTR, K_BASE |
||||
*/ |
||||
cmp K_BASE, BUFFER_PTR |
||||
jne _begin |
||||
.align 32
|
||||
jmp _end |
||||
.align 32
|
||||
_begin: |
||||
|
||||
/* |
||||
* Do first block |
||||
* rounds: 0,2,4,6,8 |
||||
*/ |
||||
.set j, 0 |
||||
.rept 5
|
||||
RR j |
||||
.set j, j+2 |
||||
.endr |
||||
|
||||
jmp _loop0 |
||||
_loop0: |
||||
|
||||
/* |
||||
* rounds: |
||||
* 10,12,14,16,18 |
||||
* 20,22,24,26,28 |
||||
* 30,32,34,36,38 |
||||
* 40,42,44,46,48 |
||||
* 50,52,54,56,58 |
||||
*/ |
||||
.rept 25
|
||||
RR j |
||||
.set j, j+2 |
||||
.endr |
||||
|
||||
add $(2*64), BUFFER_PTR /* move to next odd-64-byte block */ |
||||
cmp BUFFER_END, BUFFER_PTR /* is current block the last one? */ |
||||
cmovae K_BASE, BUFFER_PTR /* signal the last iteration smartly */ |
||||
|
||||
/* |
||||
* rounds |
||||
* 60,62,64,66,68 |
||||
* 70,72,74,76,78 |
||||
*/ |
||||
.rept 10
|
||||
RR j |
||||
.set j, j+2 |
||||
.endr |
||||
|
||||
UPDATE_HASH (HASH_PTR), A |
||||
UPDATE_HASH 4(HASH_PTR), TB |
||||
UPDATE_HASH 8(HASH_PTR), C |
||||
UPDATE_HASH 12(HASH_PTR), D |
||||
UPDATE_HASH 16(HASH_PTR), E |
||||
|
||||
cmp K_BASE, BUFFER_PTR /* is current block the last one? */ |
||||
je _loop |
||||
|
||||
mov TB, B |
||||
|
||||
/* Process second block */ |
||||
/* |
||||
* rounds |
||||
* 0+80, 2+80, 4+80, 6+80, 8+80 |
||||
* 10+80,12+80,14+80,16+80,18+80 |
||||
*/ |
||||
|
||||
.set j, 0 |
||||
.rept 10
|
||||
RR j+80 |
||||
.set j, j+2 |
||||
.endr |
||||
|
||||
jmp _loop1 |
||||
_loop1: |
||||
/* |
||||
* rounds |
||||
* 20+80,22+80,24+80,26+80,28+80 |
||||
* 30+80,32+80,34+80,36+80,38+80 |
||||
*/ |
||||
.rept 10
|
||||
RR j+80 |
||||
.set j, j+2 |
||||
.endr |
||||
|
||||
jmp _loop2 |
||||
_loop2: |
||||
|
||||
/* |
||||
* rounds |
||||
* 40+80,42+80,44+80,46+80,48+80 |
||||
* 50+80,52+80,54+80,56+80,58+80 |
||||
*/ |
||||
.rept 10
|
||||
RR j+80 |
||||
.set j, j+2 |
||||
.endr |
||||
|
||||
add $(2*64), BUFFER_PTR2 /* move to next even-64-byte block */ |
||||
|
||||
cmp BUFFER_END, BUFFER_PTR2 /* is current block the last one */ |
||||
cmovae K_BASE, BUFFER_PTR /* signal the last iteration smartly */ |
||||
|
||||
jmp _loop3 |
||||
_loop3: |
||||
|
||||
/* |
||||
* rounds |
||||
* 60+80,62+80,64+80,66+80,68+80 |
||||
* 70+80,72+80,74+80,76+80,78+80 |
||||
*/ |
||||
.rept 10
|
||||
RR j+80 |
||||
.set j, j+2 |
||||
.endr |
||||
|
||||
UPDATE_HASH (HASH_PTR), A |
||||
UPDATE_HASH 4(HASH_PTR), TB |
||||
UPDATE_HASH 8(HASH_PTR), C |
||||
UPDATE_HASH 12(HASH_PTR), D |
||||
UPDATE_HASH 16(HASH_PTR), E |
||||
|
||||
/* Reset state for AVX2 reg permutation */ |
||||
mov A, TA |
||||
mov TB, A |
||||
mov C, TB |
||||
mov E, C |
||||
mov D, B |
||||
mov TA, D |
||||
|
||||
REGALLOC |
||||
|
||||
xchg WK_BUF, PRECALC_BUF |
||||
|
||||
jmp _loop |
||||
|
||||
.align 32
|
||||
_end: |
||||
|
||||
.endm |
||||
|
||||
.section .rodata |
||||
|
||||
#define K1 0x5a827999 |
||||
#define K2 0x6ed9eba1 |
||||
#define K3 0x8f1bbcdc |
||||
#define K4 0xca62c1d6 |
||||
|
||||
.align 128
|
||||
K_XMM_AR: |
||||
.long K1, K1, K1, K1 |
||||
.long K1, K1, K1, K1 |
||||
.long K2, K2, K2, K2 |
||||
.long K2, K2, K2, K2 |
||||
.long K3, K3, K3, K3 |
||||
.long K3, K3, K3, K3 |
||||
.long K4, K4, K4, K4 |
||||
.long K4, K4, K4, K4 |
||||
|
||||
BSWAP_SHUFB_CTL: |
||||
.long 0x00010203
|
||||
.long 0x04050607
|
||||
.long 0x08090a0b
|
||||
.long 0x0c0d0e0f
|
||||
.long 0x00010203
|
||||
.long 0x04050607
|
||||
.long 0x08090a0b
|
||||
.long 0x0c0d0e0f
|
||||
|
||||
# void sha1_transform(int32_t *hash, const char* input, size_t num_blocks) ;
|
||||
.text |
||||
ENTRY(sha1_transform) |
||||
|
||||
push %rbx |
||||
push %rbp |
||||
push %r12 |
||||
push %r13 |
||||
push %r14 |
||||
push %r15 |
||||
|
||||
RESERVE_STACK = (W_SIZE*4 + 8+24) |
||||
|
||||
/* Align stack */ |
||||
mov %rsp, %rbx |
||||
and $~(0x20-1), %rsp |
||||
push %rbx |
||||
sub $RESERVE_STACK, %rsp |
||||
|
||||
avx2_zeroupper |
||||
|
||||
lea K_XMM_AR(%rip), K_BASE |
||||
|
||||
mov CTX, HASH_PTR |
||||
mov BUF, BUFFER_PTR |
||||
lea 64(BUF), BUFFER_PTR2 |
||||
|
||||
shl $6, CNT /* mul by 64 */ |
||||
add BUF, CNT |
||||
add $64, CNT |
||||
mov CNT, BUFFER_END |
||||
|
||||
cmp BUFFER_END, BUFFER_PTR2 |
||||
cmovae K_BASE, BUFFER_PTR2 |
||||
|
||||
xmm_mov BSWAP_SHUFB_CTL(%rip), YMM_SHUFB_BSWAP |
||||
|
||||
SHA1_PIPELINED_MAIN_BODY |
||||
|
||||
avx2_zeroupper |
||||
|
||||
add $RESERVE_STACK, %rsp |
||||
pop %rsp |
||||
|
||||
pop %r15 |
||||
pop %r14 |
||||
pop %r13 |
||||
pop %r12 |
||||
pop %rbp |
||||
pop %rbx |
||||
|
||||
ret |
||||
|
||||
ENDPROC(sha1_transform) |
||||
@ -0,0 +1,26 @@ |
||||
package sha1 |
||||
|
||||
import ( |
||||
. "gopkg.in/check.v1" |
||||
"testing" |
||||
) |
||||
|
||||
func Test(t *testing.T) { TestingT(t) } |
||||
|
||||
type MySuite struct{} |
||||
|
||||
var _ = Suite(&MySuite{}) |
||||
|
||||
func (s *MySuite) TestSha1(c *C) { |
||||
data_1 := []byte("Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset sheets containing Lorem Ipsum passages, and more recently with desktop publishing software like Aldus PageMaker including versions of Lorem Ipsum.") |
||||
|
||||
data_2 := []byte("Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset sheets containing Lorem Ipsum passages, and more recently with desktop publishing software like Aldus PageMaker including versions of Lorem Ipsum.") |
||||
|
||||
sha, err := Sha1(data_1) |
||||
c.Assert(err, IsNil) |
||||
|
||||
newsha, newerr := Sha1(data_2) |
||||
c.Assert(newerr, IsNil) |
||||
|
||||
c.Assert(sha, DeepEquals, newsha) |
||||
} |
||||
@ -0,0 +1,34 @@ |
||||
/* |
||||
* Mini Object Storage, (C) 2014 Minio, Inc. |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the "License"); |
||||
* you may not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an "AS IS" BASIS, |
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
// +build amd64
|
||||
|
||||
package cpu |
||||
|
||||
// #include "cpu.h"
|
||||
import "C" |
||||
|
||||
func HasSSE41() bool { |
||||
return int(C.has_sse41()) == 1 |
||||
} |
||||
|
||||
func HasAVX() bool { |
||||
return int(C.has_avx()) == 1 |
||||
} |
||||
|
||||
func HasAVX2() bool { |
||||
return int(C.has_avx2()) == 1 |
||||
} |
||||
@ -1,3 +1,19 @@ |
||||
/* |
||||
* Mini Object Storage, (C) 2014 Minio, Inc. |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the "License"); |
||||
* you may not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an "AS IS" BASIS, |
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
package cpu |
||||
|
||||
import ( |
||||
@ -1,18 +0,0 @@ |
||||
// +build amd64
|
||||
|
||||
package cpu |
||||
|
||||
// #include "cpu.h"
|
||||
import "C" |
||||
|
||||
func HasSSE41() bool { |
||||
return int(C.has_sse41()) == 1 |
||||
} |
||||
|
||||
func HasAVX() bool { |
||||
return int(C.has_avx()) == 1 |
||||
} |
||||
|
||||
func HasAVX2() bool { |
||||
return int(C.has_avx2()) == 1 |
||||
} |
||||
@ -1,23 +0,0 @@ |
||||
// +build amd64
|
||||
|
||||
package crc32c |
||||
|
||||
// #include "crc32c.h"
|
||||
import "C" |
||||
import ( |
||||
"errors" |
||||
"unsafe" |
||||
) |
||||
|
||||
func Crc32c(buffer []byte) (uint32, error) { |
||||
var length = len(buffer) |
||||
if length == 0 { |
||||
return 0, errors.New("Invalid input") |
||||
} |
||||
|
||||
var cbuf *C.uint8_t |
||||
cbuf = (*C.uint8_t)(unsafe.Pointer(&buffer[0])) |
||||
crc := C.crc32c_pcl(cbuf, C.int32_t(length), C.uint32_t(0)) |
||||
|
||||
return uint32(crc), nil |
||||
} |
||||
@ -1,3 +0,0 @@ |
||||
#include <stdint.h> |
||||
|
||||
uint32_t crc32c_pcl(uint8_t *buf, int32_t len, uint32_t prev_crc); |
||||
@ -1,24 +0,0 @@ |
||||
package crc32c |
||||
|
||||
import ( |
||||
. "gopkg.in/check.v1" |
||||
"testing" |
||||
) |
||||
|
||||
func Test(t *testing.T) { TestingT(t) } |
||||
|
||||
type MySuite struct{} |
||||
|
||||
var _ = Suite(&MySuite{}) |
||||
|
||||
func (s *MySuite) TestCrc32c(c *C) { |
||||
data_1 := []byte("Lorem Ipsum is simply dummy text of the printing and typesetting industry") |
||||
crc, err := Crc32c(data_1) |
||||
c.Assert(err, IsNil) |
||||
|
||||
data_2 := []byte("Lorem Ipsum is simply dummy text of the printing and typesetting industry") |
||||
newcrc, newerr := Crc32c(data_2) |
||||
c.Assert(newerr, IsNil) |
||||
|
||||
c.Assert(crc, Equals, newcrc) |
||||
} |
||||
Loading…
Reference in new issue