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455 lines
16 KiB
455 lines
16 KiB
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -20,6 +20,10 @@
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#include <linux/bitops.h>
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#define AR71XX_APB_BASE 0x18000000
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+#define AR71XX_GE0_BASE 0x19000000
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+#define AR71XX_GE0_SIZE 0x10000
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+#define AR71XX_GE1_BASE 0x1a000000
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+#define AR71XX_GE1_SIZE 0x10000
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#define AR71XX_EHCI_BASE 0x1b000000
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#define AR71XX_EHCI_SIZE 0x1000
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#define AR71XX_OHCI_BASE 0x1c000000
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@@ -39,6 +43,8 @@
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#define AR71XX_PLL_SIZE 0x100
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#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
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#define AR71XX_RESET_SIZE 0x100
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+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define AR71XX_MII_SIZE 0x100
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#define AR71XX_PCI_MEM_BASE 0x10000000
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#define AR71XX_PCI_MEM_SIZE 0x07000000
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@@ -81,15 +87,21 @@
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define AR933X_GMAC_SIZE 0x04
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#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR933X_WMAC_SIZE 0x20000
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#define AR933X_EHCI_BASE 0x1b000000
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#define AR933X_EHCI_SIZE 0x1000
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+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define AR934X_GMAC_SIZE 0x14
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_EHCI_BASE 0x1b000000
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#define AR934X_EHCI_SIZE 0x200
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+#define AR934X_NFC_BASE 0x1b000200
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+#define AR934X_NFC_SIZE 0xb8
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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@@ -106,11 +118,15 @@
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#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
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#define QCA955X_PCI_CTRL_SIZE 0x100
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+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define QCA955X_GMAC_SIZE 0x40
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#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define QCA955X_WMAC_SIZE 0x20000
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#define QCA955X_EHCI0_BASE 0x1b000000
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#define QCA955X_EHCI1_BASE 0x1b400000
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#define QCA955X_EHCI_SIZE 0x1000
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+#define QCA955X_NFC_BASE 0x1b800200
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+#define QCA955X_NFC_SIZE 0xb8
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#define AR9300_OTP_BASE 0x14000
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#define AR9300_OTP_STATUS 0x15f18
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@@ -181,6 +197,9 @@
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#define AR71XX_AHB_DIV_SHIFT 20
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#define AR71XX_AHB_DIV_MASK 0x7
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+#define AR71XX_ETH0_PLL_SHIFT 17
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+#define AR71XX_ETH1_PLL_SHIFT 19
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+
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#define AR724X_PLL_REG_CPU_CONFIG 0x00
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#define AR724X_PLL_REG_PCIE_CONFIG 0x10
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@@ -196,6 +215,8 @@
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
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+
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#define AR913X_PLL_REG_CPU_CONFIG 0x00
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#define AR913X_PLL_REG_ETH_CONFIG 0x04
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#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
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@@ -208,6 +229,9 @@
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#define AR913X_AHB_DIV_SHIFT 19
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#define AR913X_AHB_DIV_MASK 0x1
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+#define AR913X_ETH0_PLL_SHIFT 20
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+#define AR913X_ETH1_PLL_SHIFT 22
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+
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#define AR933X_PLL_CPU_CONFIG_REG 0x00
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#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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@@ -229,6 +253,8 @@
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#define AR934X_PLL_CPU_CONFIG_REG 0x00
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#define AR934X_PLL_DDR_CONFIG_REG 0x04
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
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+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
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+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
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#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@@ -261,9 +287,13 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
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+
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
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+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@@ -388,16 +418,83 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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+#define AR933X_RESET_GE1_MDIO BIT(23)
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+#define AR933X_RESET_GE0_MDIO BIT(22)
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+#define AR933X_RESET_GE1_MAC BIT(13)
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#define AR933X_RESET_WMAC BIT(11)
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+#define AR933X_RESET_GE0_MAC BIT(9)
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#define AR933X_RESET_USB_HOST BIT(5)
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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+#define AR934X_RESET_HOST BIT(31)
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+#define AR934X_RESET_SLIC BIT(30)
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+#define AR934X_RESET_HDMA BIT(29)
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+#define AR934X_RESET_EXTERNAL BIT(28)
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+#define AR934X_RESET_RTC BIT(27)
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+#define AR934X_RESET_PCIE_EP_INT BIT(26)
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+#define AR934X_RESET_CHKSUM_ACC BIT(25)
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+#define AR934X_RESET_FULL_CHIP BIT(24)
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+#define AR934X_RESET_GE1_MDIO BIT(23)
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+#define AR934X_RESET_GE0_MDIO BIT(22)
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+#define AR934X_RESET_CPU_NMI BIT(21)
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+#define AR934X_RESET_CPU_COLD BIT(20)
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+#define AR934X_RESET_HOST_RESET_INT BIT(19)
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+#define AR934X_RESET_PCIE_EP BIT(18)
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+#define AR934X_RESET_UART1 BIT(17)
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+#define AR934X_RESET_DDR BIT(16)
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+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
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+#define AR934X_RESET_NANDF BIT(14)
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+#define AR934X_RESET_GE1_MAC BIT(13)
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+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
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#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
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+#define AR934X_RESET_HOST_DMA_INT BIT(10)
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+#define AR934X_RESET_GE0_MAC BIT(9)
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+#define AR934X_RESET_ETH_SWITCH BIT(8)
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+#define AR934X_RESET_PCIE_PHY BIT(7)
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+#define AR934X_RESET_PCIE BIT(6)
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#define AR934X_RESET_USB_HOST BIT(5)
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#define AR934X_RESET_USB_PHY BIT(4)
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#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
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+#define AR934X_RESET_LUT BIT(2)
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+#define AR934X_RESET_MBOX BIT(1)
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+#define AR934X_RESET_I2S BIT(0)
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+
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+#define QCA955X_RESET_HOST BIT(31)
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+#define QCA955X_RESET_SLIC BIT(30)
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+#define QCA955X_RESET_HDMA BIT(29)
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+#define QCA955X_RESET_EXTERNAL BIT(28)
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+#define QCA955X_RESET_RTC BIT(27)
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+#define QCA955X_RESET_PCIE_EP_INT BIT(26)
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+#define QCA955X_RESET_CHKSUM_ACC BIT(25)
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+#define QCA955X_RESET_FULL_CHIP BIT(24)
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+#define QCA955X_RESET_GE1_MDIO BIT(23)
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+#define QCA955X_RESET_GE0_MDIO BIT(22)
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+#define QCA955X_RESET_CPU_NMI BIT(21)
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+#define QCA955X_RESET_CPU_COLD BIT(20)
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+#define QCA955X_RESET_HOST_RESET_INT BIT(19)
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+#define QCA955X_RESET_PCIE_EP BIT(18)
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+#define QCA955X_RESET_UART1 BIT(17)
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+#define QCA955X_RESET_DDR BIT(16)
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+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
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+#define QCA955X_RESET_NANDF BIT(14)
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+#define QCA955X_RESET_GE1_MAC BIT(13)
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+#define QCA955X_RESET_SGMII_ANALOG BIT(12)
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+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
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+#define QCA955X_RESET_HOST_DMA_INT BIT(10)
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+#define QCA955X_RESET_GE0_MAC BIT(9)
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+#define QCA955X_RESET_SGMII BIT(8)
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+#define QCA955X_RESET_PCIE_PHY BIT(7)
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+#define QCA955X_RESET_PCIE BIT(6)
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+#define QCA955X_RESET_USB_HOST BIT(5)
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+#define QCA955X_RESET_USB_PHY BIT(4)
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+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
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+#define QCA955X_RESET_LUT BIT(2)
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+#define QCA955X_RESET_MBOX BIT(1)
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+#define QCA955X_RESET_I2S BIT(0)
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+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
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+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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@@ -539,8 +636,22 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
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+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
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+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
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+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
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+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
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+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
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#define AR934X_GPIO_REG_FUNC 0x6c
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+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
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+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
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+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
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+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
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+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
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+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
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+#define QCA955X_GPIO_REG_FUNC 0x6c
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+
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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@@ -570,4 +681,235 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
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+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
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+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
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+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
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+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
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+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
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+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
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+
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+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
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+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
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+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
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+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
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+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
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+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
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+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
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+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
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+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
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+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
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+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
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+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
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+
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+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
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+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
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+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
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+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
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+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
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+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
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+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
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+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
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+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
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+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
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+
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+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
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+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
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+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
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+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
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+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
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+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
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+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
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+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
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+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
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+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
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+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
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+
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+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
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+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
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+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
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+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
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+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
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+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
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+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
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+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
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+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
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+
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+#define AR934X_GPIO_OUT_GPIO 0
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+#define AR934X_GPIO_OUT_SPI_CS1 7
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+#define AR934X_GPIO_OUT_LED_LINK0 41
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+#define AR934X_GPIO_OUT_LED_LINK1 42
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+#define AR934X_GPIO_OUT_LED_LINK2 43
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+#define AR934X_GPIO_OUT_LED_LINK3 44
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+#define AR934X_GPIO_OUT_LED_LINK4 45
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+#define AR934X_GPIO_OUT_EXT_LNA0 46
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+#define AR934X_GPIO_OUT_EXT_LNA1 47
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+
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+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
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+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
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+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
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+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
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+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
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+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
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+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
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+#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
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+
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+#define QCA955X_GPIO_OUT_GPIO 0
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+#define QCA955X_MII_EXT_MDI 1
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+#define QCA955X_SLIC_DATA_OUT 3
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+#define QCA955X_SLIC_PCM_FS 4
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+#define QCA955X_SLIC_PCM_CLK 5
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+#define QCA955X_SPI_CLK 8
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+#define QCA955X_SPI_CS_0 9
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+#define QCA955X_SPI_CS_1 10
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+#define QCA955X_SPI_CS_2 11
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+#define QCA955X_SPI_MISO 12
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+#define QCA955X_I2S_CLK 13
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+#define QCA955X_I2S_WS 14
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+#define QCA955X_I2S_SD 15
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+#define QCA955X_I2S_MCK 16
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+#define QCA955X_SPDIF_OUT 17
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+#define QCA955X_UART1_TD 18
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+#define QCA955X_UART1_RTS 19
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+#define QCA955X_UART1_RD 20
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+#define QCA955X_UART1_CTS 21
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+#define QCA955X_UART0_SOUT 22
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+#define QCA955X_SPDIF2_OUT 23
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+#define QCA955X_LED_SGMII_SPEED0 24
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+#define QCA955X_LED_SGMII_SPEED1 25
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+#define QCA955X_LED_SGMII_DUPLEX 26
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+#define QCA955X_LED_SGMII_LINK_UP 27
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+#define QCA955X_SGMII_SPEED0_INVERT 28
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+#define QCA955X_SGMII_SPEED1_INVERT 29
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+#define QCA955X_SGMII_DUPLEX_INVERT 30
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+#define QCA955X_SGMII_LINK_UP_INVERT 31
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+#define QCA955X_GE1_MII_MDO 32
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+#define QCA955X_GE1_MII_MDC 33
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+#define QCA955X_SWCOM2 38
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+#define QCA955X_SWCOM3 39
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+#define QCA955X_MAC2_GPIO 40
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+#define QCA955X_MAC3_GPIO 41
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+#define QCA955X_ATT_LED 42
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+#define QCA955X_PWR_LED 43
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+#define QCA955X_TX_FRAME 44
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+#define QCA955X_RX_CLEAR_EXTERNAL 45
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+#define QCA955X_LED_NETWORK_EN 46
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+#define QCA955X_LED_POWER_EN 47
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+#define QCA955X_WMAC_GLUE_WOW 68
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+#define QCA955X_RX_CLEAR_EXTENSION 70
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+#define QCA955X_CP_NAND_CS1 73
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+#define QCA955X_USB_SUSPEND 74
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+#define QCA955X_ETH_TX_ERR 75
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+#define QCA955X_DDR_DQ_OE 76
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+#define QCA955X_CLKREQ_N_EP 77
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+#define QCA955X_CLKREQ_N_RC 78
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+#define QCA955X_CLK_OBS0 79
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+#define QCA955X_CLK_OBS1 80
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+#define QCA955X_CLK_OBS2 81
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+#define QCA955X_CLK_OBS3 82
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+#define QCA955X_CLK_OBS4 83
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+#define QCA955X_CLK_OBS5 84
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+
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+/*
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+ * MII_CTRL block
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+ */
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+#define AR71XX_MII_REG_MII0_CTRL 0x00
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+#define AR71XX_MII_REG_MII1_CTRL 0x04
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+
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+#define AR71XX_MII_CTRL_IF_MASK 3
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+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
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+#define AR71XX_MII_CTRL_SPEED_MASK 3
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+#define AR71XX_MII_CTRL_SPEED_10 0
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+#define AR71XX_MII_CTRL_SPEED_100 1
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+#define AR71XX_MII_CTRL_SPEED_1000 2
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+
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+#define AR71XX_MII0_CTRL_IF_GMII 0
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+#define AR71XX_MII0_CTRL_IF_MII 1
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+#define AR71XX_MII0_CTRL_IF_RGMII 2
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+#define AR71XX_MII0_CTRL_IF_RMII 3
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+
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+#define AR71XX_MII1_CTRL_IF_RGMII 0
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+#define AR71XX_MII1_CTRL_IF_RMII 1
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+
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+/*
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+ * AR933X GMAC interface
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+ */
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+#define AR933X_GMAC_REG_ETH_CFG 0x00
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+
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+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
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+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
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+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
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+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
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+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
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+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
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+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
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+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
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+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
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+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
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+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
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+
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+/*
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+ * AR934X GMAC Interface
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+ */
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+#define AR934X_GMAC_REG_ETH_CFG 0x00
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+
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+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
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+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
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+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
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+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
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+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
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+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
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+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
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+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
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+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
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+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
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+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
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+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
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+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
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+#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
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+#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
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+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
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+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
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+
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+/*
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+ * QCA955X GMAC Interface
|
|
+ */
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+
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+#define QCA955X_GMAC_REG_ETH_CFG 0x00
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+
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+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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+#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
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+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
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+#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
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|
+#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
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|
+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
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|
+#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
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|
+#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
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|
+#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
|
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+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
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|
+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
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|
+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
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|
+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
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|
+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
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|
+#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
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|
+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
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|
+#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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|
+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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+
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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