7 Commits (73f7a1c224f037ba0cbca1dcf71d56de7e25a731)

Author SHA1 Message Date
Gabor Juhos 73f7a1c224 ar71xx: optimize register access in ar71xx_pci.c 15 years ago
Gabor Juhos 5f109ef2f3 ar71xx: move PCI intterupt handling code to pci-ar7{1xx,24x}.c 15 years ago
Gabor Juhos 0757fee42d ar71xx: use ar71xx_pci_fixup on ar71xx SoCs only 15 years ago
Gabor Juhos 089b5ccb47 reorganize PCI code 16 years ago
Gabor Juhos 9f93bd51cf rename DDR registers 16 years ago
Gabor Juhos a43e2d5ac6 fix the PCI byte lane enable generation code, based on a patch by Chris Dearman 16 years ago
Gabor Juhos f529a37420 surprise :p 17 years ago