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@ -59,17 +59,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val) |
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/* Byte lane enable bits */ |
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static u8 ble_table[4][4] = { |
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{0xf, 0xe, 0xd, 0xc}, |
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{0xc, 0x9, 0x3, 0x1}, |
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{0x0, 0x0, 0x0, 0x0}, |
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{0x0, 0x0, 0x0, 0x0}, |
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{0x0, 0xf, 0xf, 0xf}, |
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{0xe, 0xd, 0xb, 0x7}, |
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{0xc, 0xf, 0x3, 0xf}, |
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{0xf, 0xf, 0xf, 0xf}, |
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}; |
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static inline u32 ar71xx_pci_get_ble(int where, int size, int local) |
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{ |
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u32 t; |
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t = ble_table[size][where & 3]; |
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t = ble_table[size & 3][where & 3]; |
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BUG_ON(t == 0xf); |
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t <<= (local) ? 20 : 4; |
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return t; |
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} |
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