13 Commits (1be47feb2ef90b890aa80cfd2a8e5010e94dc89b)

Author SHA1 Message Date
Florian Fainelli 5a7c5b2d36 a couple of more fixes to get 6345 booting up to the console handover 15 years ago
Florian Fainelli 13a8ed9ca0 more missing register definitions for bcm6338 15 years ago
Florian Fainelli 287a2c0ba9 more bcm6338 and bcm6345 related fixes 15 years ago
Florian Fainelli 8c4137900c define bcm6338 SDRAM base register and make sure that the right CPU id will be used to detect a bcm6338 15 years ago
Florian Fainelli 0972ee5331 add support for bcm6345 SoC, needs testing 16 years ago
Florian Fainelli 32c29f1aaf fix SPI register switch and prepare for UDC, thanks to Henk Vergonet (#4783) 16 years ago
Florian Fainelli 1bcf5d0de6 fix typo for the bcm6338 spi IRQ, change platform driver name and make the SPI irq be fetchable by platform driver initialization code 16 years ago
Florian Fainelli 1e92d0355d make bcm6358 consistend with the other boards naming 16 years ago
Florian Fainelli 5e8dfe53b6 prepare for SPI controller driver 16 years ago
Florian Fainelli 46b91ed787 frequency is in Hz, thanks Joel 16 years ago
Florian Fainelli 5905a48169 allow bcm6338 to get the base address of the memory controller register, required to detect memory size 16 years ago
Florian Fainelli 3dd67d64f4 add experimental support for bcm6338 16 years ago
Florian Fainelli 1c77ec0587 Flatten brcm63xx patches, should make our life easier to patch files now ;) 16 years ago