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@ -123,21 +123,30 @@ enum bcm63xx_regs_set { |
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#define BCM_6338_DSL_LMEM_BASE (0xfff00000) |
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#define BCM_6338_PERF_BASE (0xfffe0000) |
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#define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */ |
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#define BCM_6338_BB_BASE (0xdeadbeef) |
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#define BCM_6338_TIMER_BASE (0xfffe0200) |
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#define BCM_6338_WDT_BASE (0xfffe021c) |
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#define BCM_6338_UART0_BASE (0xfffe0300) |
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#define BCM_6338_GPIO_BASE (0xfffe0400) |
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#define BCM_6338_SPI_BASE (0xfffe0c00) |
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#define BCM_6338_UDC0_BASE (0xdeadbeef) |
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#define BCM_6338_USBDMA_BASE (0xfffe2400) |
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#define BCM_6338_OHCI0_BASE (0xdeadbeef) |
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#define BCM_6338_OHCI_PRIV_BASE (0xdeadbeef) |
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) |
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#define BCM_6338_MPI_BASE (0xdeadbeef) |
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef) |
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) |
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#define BCM_6338_DSL_BASE (0xfffe1000) |
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#define BCM_6338_SAR_BASE (0xfffe2000) |
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#define BCM_6338_ENETDMA_BASE (0xfffe2400) |
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#define BCM_6338_USBDMA_BASE (0xfffe2400) |
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#define BCM_6338_UBUS_BASE (0xdeadbeef) |
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#define BCM_6338_ENET0_BASE (0xfffe2800) |
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#define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */ |
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) |
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#define BCM_6338_ENET1_BASE (0xdeadbeef) |
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#define BCM_6338_ENETDMA_BASE (0xfffe3800) |
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#define BCM_6338_EHCI0_BASE (0xdeadbeef) |
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#define BCM_6338_SDRAM_BASE (0xfffe3100) |
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#define BCM_6338_MEMC_BASE (0xdeadbeef) |
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#define BCM_6338_DDR_BASE (0xdeadbeef) |
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/*
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* 6345 register sets base address |
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@ -228,10 +237,34 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) |
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return BCM_6338_GPIO_BASE; |
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case RSET_SPI: |
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return BCM_6338_SPI_BASE; |
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case RSET_MEMC: |
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return BCM_6338_MEMC_BASE; |
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case RSET_UDC0: |
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return BCM_6338_UDC0_BASE; |
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case RSET_OHCI0: |
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return BCM_6338_OHCI0_BASE; |
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case RSET_OHCI_PRIV: |
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return BCM_6338_OHCI_PRIV_BASE; |
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case RSET_USBH_PRIV: |
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return BCM_6338_USBH_PRIV_BASE; |
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case RSET_MPI: |
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return BCM_6338_MPI_BASE; |
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case RSET_PCMCIA: |
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return BCM_6338_PCMCIA_BASE; |
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case RSET_DSL: |
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return BCM_6338_DSL_BASE; |
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case RSET_ENET0: |
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return BCM_6338_ENET0_BASE; |
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case RSET_ENET1: |
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return BCM_6338_ENET1_BASE; |
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case RSET_ENETDMA: |
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return BCM_6338_ENETDMA_BASE; |
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case RSET_EHCI0: |
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return BCM_6338_EHCI0_BASE; |
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case RSET_SDRAM: |
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return BCM_6338_SDRAM_BASE; |
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case RSET_MEMC: |
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return BCM_6338_MEMC_BASE; |
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case RSET_DDR: |
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return BCM_6338_DDR_BASE; |
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} |
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#endif |
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#ifdef CONFIG_BCM63XX_CPU_6345 |
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