|
|
|
@ -458,7 +458,7 @@ |
|
|
|
|
/*
|
|
|
|
|
--- a/arch/mips/mm/tlbex.c
|
|
|
|
|
+++ b/arch/mips/mm/tlbex.c
|
|
|
|
|
@@ -971,6 +971,9 @@ void build_get_pgde32(u32 **p, unsigned
|
|
|
|
|
@@ -976,6 +976,9 @@ void build_get_pgde32(u32 **p, unsigned
|
|
|
|
|
uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
|
|
|
|
|
uasm_i_addu(p, ptr, tmp, ptr);
|
|
|
|
|
#else
|
|
|
|
@ -468,7 +468,7 @@ |
|
|
|
|
UASM_i_LA_mostly(p, ptr, pgdc);
|
|
|
|
|
#endif
|
|
|
|
|
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
|
|
|
|
|
@@ -1331,6 +1334,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
|
|
@@ -1337,6 +1340,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
|
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
|
|
|
|
#else
|
|
|
|
@ -478,7 +478,7 @@ |
|
|
|
|
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
@@ -1342,6 +1348,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
|
|
@@ -1348,6 +1354,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
|
|
build_update_entries(&p, K0, K1);
|
|
|
|
|
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
|
|
|
|
uasm_l_leave(&l, p);
|
|
|
|
@ -488,7 +488,7 @@ |
|
|
|
|
uasm_i_eret(&p); /* return from trap */
|
|
|
|
|
}
|
|
|
|
|
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
|
|
|
|
|
@@ -2046,6 +2055,9 @@ build_r4000_tlbchange_handler_head(u32 *
|
|
|
|
|
@@ -2057,6 +2066,9 @@ build_r4000_tlbchange_handler_head(u32 *
|
|
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
|
build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
|
|
|
|
|
#else
|
|
|
|
@ -498,7 +498,7 @@ |
|
|
|
|
build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
@@ -2092,6 +2104,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
|
|
|
|
@@ -2103,6 +2115,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
|
|
|
|
build_tlb_write_entry(p, l, r, tlb_indexed);
|
|
|
|
|
uasm_l_leave(l, *p);
|
|
|
|
|
build_restore_work_registers(p);
|
|
|
|
|