List of patches that Jo-Philipp groveled out of git. Redux: defuzzed. Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com> SVN-Revision: 30366master
Jo-Philipp Wich
13 years ago
parent
5609ad736e
commit
f35c4a3266
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From b189e810619a676e6b931a942a3e8387f3d39c21 Mon Sep 17 00:00:00 2001
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From: =?utf8?q?fran=C3=A7ois=20romieu?= <romieu@fr.zoreil.com>
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Date: Sun, 8 Jan 2012 13:41:33 +0000
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Subject: [PATCH] 8139cp: fix missing napi_gro_flush.
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The driver uses __napi_complete and napi_gro_receive. Without it, the
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driver hits the BUG_ON(n->gro_list) assertion hard in __napi_complete.
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Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
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Tested-by: Marin Glibic <zhilla2@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/realtek/8139cp.c | 1 +
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1 files changed, 1 insertions(+), 0 deletions(-)
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--- a/drivers/net/ethernet/realtek/8139cp.c
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+++ b/drivers/net/ethernet/realtek/8139cp.c
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@@ -563,6 +563,7 @@ rx_next:
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if (cpr16(IntrStatus) & cp_rx_intr_mask)
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goto rx_status_loop;
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+ napi_gro_flush(napi);
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spin_lock_irqsave(&cp->lock, flags);
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__napi_complete(napi);
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cpw16_f(IntrMask, cp_intr_mask);
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@ -0,0 +1,37 @@ |
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From 7d03f5a48e4d90854275b06433626243b3b3db17 Mon Sep 17 00:00:00 2001
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From: Jason Wang <jasowang@redhat.com>
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Date: Fri, 30 Dec 2011 23:44:33 +0000
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Subject: [PATCH] 8139cp/8139too: do not read into reserved registers
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delay_eeprom() use long read for Cfg9346 register(offset 0x50) which may read
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into the area of reserved register(offset 0x53). Use byte read instead.
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Signed-off-by: Jason Wang <jasowang@redhat.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/realtek/8139cp.c | 2 +-
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drivers/net/ethernet/realtek/8139too.c | 2 +-
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2 files changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/net/ethernet/realtek/8139cp.c
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+++ b/drivers/net/ethernet/realtek/8139cp.c
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@@ -1590,7 +1590,7 @@ static int cp_set_mac_address(struct net
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No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
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*/
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-#define eeprom_delay() readl(ee_addr)
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+#define eeprom_delay() readb(ee_addr)
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_EXTEND_CMD (4)
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--- a/drivers/net/ethernet/realtek/8139too.c
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+++ b/drivers/net/ethernet/realtek/8139too.c
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@@ -1122,7 +1122,7 @@ static void __devexit rtl8139_remove_one
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No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
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*/
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-#define eeprom_delay() (void)RTL_R32(Cfg9346)
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+#define eeprom_delay() (void)RTL_R8(Cfg9346)
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_WRITE_CMD (5)
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@ -0,0 +1,45 @@ |
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From f872b237c1750221932e715da2552225afe4a95c Mon Sep 17 00:00:00 2001
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From: Jason Wang <jasowang@redhat.com>
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Date: Fri, 30 Dec 2011 23:44:42 +0000
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Subject: [PATCH] 8139cp: properly config rx mode after resuming
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Rx mode should be reset after resming, so unconditionally updating rx
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mode rather than conditionally updating based on the value we
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remembered, otherwise unexpected value may be used by the nic after
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resuming.
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btw. I find and test this when debugging guest hibernation in qemu, as
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I did not have a 8139cp card in hand, this patch is untested in a
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physical 8139cp card, plase review it carefully.
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Signed-off-by: Jason Wang <jasowang@redhat.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/realtek/8139cp.c | 9 +++------
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1 files changed, 3 insertions(+), 6 deletions(-)
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--- a/drivers/net/ethernet/realtek/8139cp.c
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+++ b/drivers/net/ethernet/realtek/8139cp.c
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@@ -860,7 +860,6 @@ static void __cp_set_rx_mode (struct net
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struct cp_private *cp = netdev_priv(dev);
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u32 mc_filter[2]; /* Multicast hash filter */
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int rx_mode;
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- u32 tmp;
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/* Note: do not reorder, GCC is clever about common statements. */
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if (dev->flags & IFF_PROMISC) {
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@@ -887,11 +886,9 @@ static void __cp_set_rx_mode (struct net
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}
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/* We can safely update without stopping the chip. */
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- tmp = cp_rx_config | rx_mode;
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- if (cp->rx_config != tmp) {
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- cpw32_f (RxConfig, tmp);
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- cp->rx_config = tmp;
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- }
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+ cp->rx_config = cp_rx_config | rx_mode;
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+ cpw32_f(RxConfig, cp->rx_config);
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+
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cpw32_f (MAR0 + 0, mc_filter[0]);
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cpw32_f (MAR0 + 4, mc_filter[1]);
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}
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