Make the dts file match with what is upstream, to ensure it has the latest changes and switching to newer kernels is easier. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Acked-by: Felix Fietkau <nbd@nbd.name>master
parent
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f2102b484b
@ -1,456 +0,0 @@ |
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/* |
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* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828) |
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* |
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* Copyright (C) 2015 Russell King |
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* |
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* This board is in development; the contents of this file work with |
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* the A1 rev 2.0 of the board, which does not represent final |
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* production board. Things will change, don't expect this file to |
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* remain compatible info the future. |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* version 2 as published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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/dts-v1/; |
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#include "armada-388.dtsi" |
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#include "armada-38x-solidrun-microsom.dtsi" |
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/ { |
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model = "SolidRun Clearfog A1"; |
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compatible = "solidrun,clearfog-a1", "marvell,armada388", |
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"marvell,armada385", "marvell,armada380"; |
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aliases { |
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/* So that mvebu u-boot can update the MAC addresses */ |
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ethernet1 = ð0; |
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ethernet2 = ð1; |
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ethernet3 = ð2; |
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}; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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reg_3p3v: regulator-3p3v { |
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compatible = "regulator-fixed"; |
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regulator-name = "3P3V"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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soc { |
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internal-regs { |
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ethernet@30000 { |
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phy-mode = "sgmii"; |
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status = "okay"; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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}; |
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}; |
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ethernet@34000 { |
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phy-mode = "sgmii"; |
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status = "okay"; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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}; |
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}; |
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i2c@11000 { |
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/* Is there anything on this? */ |
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clock-frequency = <100000>; |
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pinctrl-0 = <&i2c0_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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/* |
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* PCA9655 GPIO expander, up to 1MHz clock. |
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* 0-CON3 CLKREQ# |
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* 1-CON3 PERST# |
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* 2-CON2 PERST# |
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* 3-CON3 W_DISABLE |
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* 4-CON2 CLKREQ# |
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* 5-USB3 overcurrent |
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* 6-USB3 power |
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* 7-CON2 W_DISABLE |
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* 8-JP4 P1 |
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* 9-JP4 P4 |
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* 10-JP4 P5 |
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* 11-m.2 DEVSLP |
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* 12-SFP_LOS |
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* 13-SFP_TX_FAULT |
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* 14-SFP_TX_DISABLE |
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* 15-SFP_MOD_DEF0 |
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*/ |
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expander0: gpio-expander@20 { |
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/* |
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* This is how it should be: |
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* compatible = "onnn,pca9655", |
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* "nxp,pca9555"; |
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* but you can't do this because of |
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* the way I2C works. |
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*/ |
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compatible = "nxp,pca9555"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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reg = <0x20>; |
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pcie1_0_clkreq { |
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gpio-hog; |
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gpios = <0 GPIO_ACTIVE_LOW>; |
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input; |
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line-name = "pcie1.0-clkreq"; |
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}; |
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pcie1_0_w_disable { |
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gpio-hog; |
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gpios = <3 GPIO_ACTIVE_LOW>; |
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output-low; |
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line-name = "pcie1.0-w-disable"; |
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}; |
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pcie2_0_clkreq { |
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gpio-hog; |
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gpios = <4 GPIO_ACTIVE_LOW>; |
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input; |
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line-name = "pcie2.0-clkreq"; |
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}; |
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pcie2_0_w_disable { |
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gpio-hog; |
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gpios = <7 GPIO_ACTIVE_LOW>; |
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output-low; |
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line-name = "pcie2.0-w-disable"; |
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}; |
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usb3_ilimit { |
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gpio-hog; |
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gpios = <5 GPIO_ACTIVE_LOW>; |
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input; |
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line-name = "usb3-current-limit"; |
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}; |
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usb3_power { |
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gpio-hog; |
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gpios = <6 GPIO_ACTIVE_HIGH>; |
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output-high; |
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line-name = "usb3-power"; |
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}; |
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m2_devslp { |
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gpio-hog; |
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gpios = <11 GPIO_ACTIVE_HIGH>; |
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output-low; |
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line-name = "m.2 devslp"; |
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}; |
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sfp_los { |
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/* SFP loss of signal */ |
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gpio-hog; |
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gpios = <12 GPIO_ACTIVE_HIGH>; |
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input; |
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line-name = "sfp-los"; |
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}; |
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sfp_tx_fault { |
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/* SFP laser fault */ |
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gpio-hog; |
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gpios = <13 GPIO_ACTIVE_HIGH>; |
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input; |
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line-name = "sfp-tx-fault"; |
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}; |
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sfp_tx_disable { |
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/* SFP transmit disable */ |
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gpio-hog; |
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gpios = <14 GPIO_ACTIVE_HIGH>; |
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output-low; |
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line-name = "sfp-tx-disable"; |
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}; |
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sfp_mod_def0 { |
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/* SFP module present */ |
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gpio-hog; |
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gpios = <15 GPIO_ACTIVE_LOW>; |
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input; |
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line-name = "sfp-mod-def0"; |
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}; |
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}; |
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/* The MCP3021 is 100kHz clock only */ |
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mikrobus_adc: mcp3021@4c { |
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compatible = "microchip,mcp3021"; |
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reg = <0x4c>; |
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}; |
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/* Also something at 0x64 */ |
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}; |
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i2c@11100 { |
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/* |
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* Routed to SFP, mikrobus, and PCIe. |
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* SFP limits this to 100kHz, and requires |
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* an AT24C01A/02/04 with address pins tied |
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* low, which takes addresses 0x50 and 0x51. |
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* Mikrobus doesn't specify beyond an I2C |
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* bus being present. |
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* PCIe uses ARP to assign addresses, or |
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* 0x63-0x64. |
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*/ |
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clock-frequency = <100000>; |
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pinctrl-0 = <&clearfog_i2c1_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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mdio@72004 { |
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pinctrl-0 = <&mdio_pins>; |
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pinctrl-names = "default"; |
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phy_dedicated: ethernet-phy@0 { |
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/* |
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* Annoyingly, the marvell phy driver |
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* configures the LED register, rather |
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* than preserving reset-loaded setting. |
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* We undo that rubbish here. |
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*/ |
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marvell,reg-init = <3 16 0 0x101e>; |
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reg = <0>; |
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}; |
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}; |
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pinctrl@18000 { |
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clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { |
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marvell,pins = "mpp46"; |
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marvell,function = "ref"; |
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}; |
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clearfog_dsa0_pins: clearfog-dsa0-pins { |
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marvell,pins = "mpp23", "mpp41"; |
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marvell,function = "gpio"; |
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}; |
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clearfog_i2c1_pins: i2c1-pins { |
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/* SFP, PCIe, mSATA, mikrobus */ |
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marvell,pins = "mpp26", "mpp27"; |
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marvell,function = "i2c1"; |
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}; |
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clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { |
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marvell,pins = "mpp20"; |
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marvell,function = "gpio"; |
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}; |
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clearfog_sdhci_pins: clearfog-sdhci-pins { |
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marvell,pins = "mpp21", "mpp28", |
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"mpp37", "mpp38", |
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"mpp39", "mpp40"; |
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marvell,function = "sd0"; |
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}; |
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clearfog_spi1_cs_pins: spi1-cs-pins { |
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marvell,pins = "mpp55"; |
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marvell,function = "spi1"; |
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}; |
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mikro_pins: mikro-pins { |
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/* int: mpp22 rst: mpp29 */ |
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marvell,pins = "mpp22", "mpp29"; |
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marvell,function = "gpio"; |
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}; |
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mikro_spi_pins: mikro-spi-pins { |
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marvell,pins = "mpp43"; |
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marvell,function = "spi1"; |
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}; |
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mikro_uart_pins: mikro-uart-pins { |
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marvell,pins = "mpp24", "mpp25"; |
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marvell,function = "ua1"; |
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}; |
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rear_button_pins: rear-button-pins { |
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marvell,pins = "mpp34"; |
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marvell,function = "gpio"; |
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}; |
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}; |
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sata@a8000 { |
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/* pinctrl? */ |
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status = "okay"; |
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}; |
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sata@e0000 { |
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/* pinctrl? */ |
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status = "okay"; |
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}; |
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sdhci@d8000 { |
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bus-width = <4>; |
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cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; |
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no-1-8-v; |
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pinctrl-0 = <&clearfog_sdhci_pins |
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&clearfog_sdhci_cd_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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vmmc = <®_3p3v>; |
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wp-inverted; |
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}; |
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serial@12100 { |
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/* mikrobus uart */ |
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pinctrl-0 = <&mikro_uart_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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spi@10680 { |
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/* |
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* We don't seem to have the W25Q32 on the |
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* A1 Rev 2.0 boards, so disable SPI. |
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* CS0: W25Q32 (doesn't appear to be present) |
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* CS1: |
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* CS2: mikrobus |
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*/ |
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pinctrl-0 = <&spi1_pins |
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&clearfog_spi1_cs_pins |
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&mikro_spi_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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spi-flash@0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "w25q32", "jedec,spi-nor"; |
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reg = <0>; /* Chip select 0 */ |
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spi-max-frequency = <3000000>; |
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status = "disabled"; |
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}; |
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}; |
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usb@58000 { |
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/* CON3, nearest power. */ |
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status = "okay"; |
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}; |
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usb3@f0000 { |
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/* CON2, nearest CPU, USB2 only. */ |
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status = "okay"; |
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}; |
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usb3@f8000 { |
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/* CON7 */ |
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status = "okay"; |
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}; |
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}; |
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pcie-controller { |
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status = "okay"; |
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/* |
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* The two PCIe units are accessible through |
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* the mini-PCIe connectors on the board. |
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*/ |
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pcie@2,0 { |
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/* Port 1, Lane 0. CON3, nearest power. */ |
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reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; |
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status = "okay"; |
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}; |
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pcie@3,0 { |
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/* Port 2, Lane 0. CON2, nearest CPU. */ |
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reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; |
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status = "okay"; |
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}; |
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}; |
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}; |
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dsa@0 { |
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compatible = "marvell,dsa"; |
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dsa,ethernet = <ð1>; |
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dsa,mii-bus = <&mdio>; |
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pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; |
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pinctrl-names = "default"; |
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#address-cells = <2>; |
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#size-cells = <0>; |
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switch@0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <4 0>; |
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port@0 { |
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reg = <0>; |
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label = "lan1"; |
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}; |
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port@1 { |
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reg = <1>; |
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label = "lan2"; |
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}; |
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port@2 { |
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reg = <2>; |
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label = "lan3"; |
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}; |
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port@3 { |
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reg = <3>; |
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label = "lan4"; |
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}; |
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port@4 { |
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reg = <4>; |
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label = "lan5"; |
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}; |
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port@5 { |
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reg = <5>; |
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label = "cpu"; |
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||||||
}; |
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||||||
|
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port@6 { |
|
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/* 88E1512 external phy */ |
|
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reg = <6>; |
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label = "lan6"; |
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fixed-link { |
|
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speed = <1000>; |
|
||||||
full-duplex; |
|
||||||
}; |
|
||||||
}; |
|
||||||
}; |
|
||||||
}; |
|
||||||
|
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||||||
gpio-keys { |
|
||||||
compatible = "gpio-keys"; |
|
||||||
pinctrl-0 = <&rear_button_pins>; |
|
||||||
pinctrl-names = "default"; |
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|
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||||||
button_0 { |
|
||||||
/* The rear SW3 button */ |
|
||||||
label = "Rear Button"; |
|
||||||
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; |
|
||||||
linux,can-disable; |
|
||||||
linux,code = <BTN_0>; |
|
||||||
}; |
|
||||||
}; |
|
||||||
}; |
|
@ -1,115 +0,0 @@ |
|||||||
/* |
|
||||||
* Device Tree file for SolidRun Armada 38x Microsom |
|
||||||
* |
|
||||||
* Copyright (C) 2015 Russell King |
|
||||||
* |
|
||||||
* This board is in development; the contents of this file work with |
|
||||||
* the A1 rev 2.0 of the board, which does not represent final |
|
||||||
* production board. Things will change, don't expect this file to |
|
||||||
* remain compatible info the future. |
|
||||||
* |
|
||||||
* This file is dual-licensed: you can use it either under the terms |
|
||||||
* of the GPL or the X11 license, at your option. Note that this dual |
|
||||||
* licensing only applies to this file, and not this project as a |
|
||||||
* whole. |
|
||||||
* |
|
||||||
* a) This file is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License |
|
||||||
* version 2 as published by the Free Software Foundation. |
|
||||||
* |
|
||||||
* This file is distributed in the hope that it will be useful |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* Or, alternatively |
|
||||||
* |
|
||||||
* b) Permission is hereby granted, free of charge, to any person |
|
||||||
* obtaining a copy of this software and associated documentation |
|
||||||
* files (the "Software"), to deal in the Software without |
|
||||||
* restriction, including without limitation the rights to use |
|
||||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
|
||||||
* sell copies of the Software, and to permit persons to whom the |
|
||||||
* Software is furnished to do so, subject to the following |
|
||||||
* conditions: |
|
||||||
* |
|
||||||
* The above copyright notice and this permission notice shall be |
|
||||||
* included in all copies or substantial portions of the Software. |
|
||||||
* |
|
||||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
|
||||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
|
||||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
|
||||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
|
||||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
|
||||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
|
||||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
|
||||||
* OTHER DEALINGS IN THE SOFTWARE. |
|
||||||
*/ |
|
||||||
#include <dt-bindings/input/input.h> |
|
||||||
#include <dt-bindings/gpio/gpio.h> |
|
||||||
|
|
||||||
/ { |
|
||||||
memory { |
|
||||||
device_type = "memory"; |
|
||||||
reg = <0x00000000 0x10000000>; /* 256 MB */ |
|
||||||
}; |
|
||||||
|
|
||||||
soc { |
|
||||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 |
|
||||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 |
|
||||||
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 |
|
||||||
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; |
|
||||||
|
|
||||||
internal-regs { |
|
||||||
ethernet@70000 { |
|
||||||
pinctrl-0 = <&ge0_rgmii_pins>; |
|
||||||
pinctrl-names = "default"; |
|
||||||
phy = <&phy_dedicated>; |
|
||||||
phy-mode = "rgmii-id"; |
|
||||||
status = "okay"; |
|
||||||
}; |
|
||||||
|
|
||||||
mdio@72004 { |
|
||||||
/* |
|
||||||
* Add the phy clock here, so the phy can be |
|
||||||
* accessed to read its IDs prior to binding |
|
||||||
* with the driver. |
|
||||||
*/ |
|
||||||
pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; |
|
||||||
pinctrl-names = "default"; |
|
||||||
|
|
||||||
phy_dedicated: ethernet-phy@0 { |
|
||||||
/* |
|
||||||
* Annoyingly, the marvell phy driver |
|
||||||
* configures the LED register, rather |
|
||||||
* than preserving reset-loaded setting. |
|
||||||
* We undo that rubbish here. |
|
||||||
*/ |
|
||||||
marvell,reg-init = <3 16 0 0x101e>; |
|
||||||
reg = <0>; |
|
||||||
}; |
|
||||||
}; |
|
||||||
|
|
||||||
pinctrl@18000 { |
|
||||||
microsom_phy_clk_pins: microsom-phy-clk-pins { |
|
||||||
marvell,pins = "mpp45"; |
|
||||||
marvell,function = "ref"; |
|
||||||
}; |
|
||||||
}; |
|
||||||
|
|
||||||
rtc@a3800 { |
|
||||||
/* |
|
||||||
* If the rtc doesn't work, run "date reset" |
|
||||||
* twice in u-boot. |
|
||||||
*/ |
|
||||||
status = "okay"; |
|
||||||
}; |
|
||||||
|
|
||||||
serial@12000 { |
|
||||||
pinctrl-0 = <&uart0_pins>; |
|
||||||
pinctrl-names = "default"; |
|
||||||
status = "okay"; |
|
||||||
}; |
|
||||||
}; |
|
||||||
}; |
|
||||||
}; |
|
@ -0,0 +1,611 @@ |
|||||||
|
From 4c945e8556ec7ea5b19d4f8721b212f468656e0d Mon Sep 17 00:00:00 2001
|
||||||
|
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||||
|
Date: Sun, 6 Dec 2015 21:52:06 +0000
|
||||||
|
Subject: [PATCH] ARM: dts: Add SolidRun Armada 388 Clearfog A1 DT file
|
||||||
|
|
||||||
|
Add support for the SolidRun Armada 388 Clearfog A1 board. This board
|
||||||
|
has an Armada 388 microsom, dedicated gigabit ethernet, six switched
|
||||||
|
gigabit ethernet ports, SFP cage, two Mini-PCIe/mSATA slots, a m.2 SATA
|
||||||
|
slot, and a MikroBUS connector to allow MikroBUS modules to be added.
|
||||||
|
|
||||||
|
This DT file adds support for all board facilities with the exception
|
||||||
|
of full SFP support.
|
||||||
|
|
||||||
|
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||||
|
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||||
|
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/Makefile | 1 +
|
||||||
|
arch/arm/boot/dts/armada-388-clearfog.dts | 456 +++++++++++++++++++++
|
||||||
|
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 115 ++++++
|
||||||
|
3 files changed, 572 insertions(+)
|
||||||
|
create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dts
|
||||||
|
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/Makefile
|
||||||
|
+++ b/arch/arm/boot/dts/Makefile
|
||||||
|
@@ -749,6 +749,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
|
||||||
|
armada-385-linksys-caiman.dtb \
|
||||||
|
armada-385-linksys-cobra.dtb \
|
||||||
|
armada-385-linksys-shelby.dtb \
|
||||||
|
+ armada-388-clearfog.dtb \
|
||||||
|
armada-388-db.dtb \
|
||||||
|
armada-388-gp.dtb \
|
||||||
|
armada-388-rd.dtb
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||||
|
@@ -0,0 +1,456 @@
|
||||||
|
+/*
|
||||||
|
+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2015 Russell King
|
||||||
|
+ *
|
||||||
|
+ * This board is in development; the contents of this file work with
|
||||||
|
+ * the A1 rev 2.0 of the board, which does not represent final
|
||||||
|
+ * production board. Things will change, don't expect this file to
|
||||||
|
+ * remain compatible info the future.
|
||||||
|
+ *
|
||||||
|
+ * This file is dual-licensed: you can use it either under the terms
|
||||||
|
+ * of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
+ * licensing only applies to this file, and not this project as a
|
||||||
|
+ * whole.
|
||||||
|
+ *
|
||||||
|
+ * a) This file is free software; you can redistribute it and/or
|
||||||
|
+ * modify it under the terms of the GNU General Public License
|
||||||
|
+ * version 2 as published by the Free Software Foundation.
|
||||||
|
+ *
|
||||||
|
+ * This file is distributed in the hope that it will be useful
|
||||||
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+ * GNU General Public License for more details.
|
||||||
|
+ *
|
||||||
|
+ * Or, alternatively
|
||||||
|
+ *
|
||||||
|
+ * b) Permission is hereby granted, free of charge, to any person
|
||||||
|
+ * obtaining a copy of this software and associated documentation
|
||||||
|
+ * files (the "Software"), to deal in the Software without
|
||||||
|
+ * restriction, including without limitation the rights to use
|
||||||
|
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
+ * sell copies of the Software, and to permit persons to whom the
|
||||||
|
+ * Software is furnished to do so, subject to the following
|
||||||
|
+ * conditions:
|
||||||
|
+ *
|
||||||
|
+ * The above copyright notice and this permission notice shall be
|
||||||
|
+ * included in all copies or substantial portions of the Software.
|
||||||
|
+ *
|
||||||
|
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||||
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||||
|
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
+ * OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+/dts-v1/;
|
||||||
|
+#include "armada-388.dtsi"
|
||||||
|
+#include "armada-38x-solidrun-microsom.dtsi"
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ model = "SolidRun Clearfog A1";
|
||||||
|
+ compatible = "solidrun,clearfog-a1", "marvell,armada388",
|
||||||
|
+ "marvell,armada385", "marvell,armada380";
|
||||||
|
+
|
||||||
|
+ aliases {
|
||||||
|
+ /* So that mvebu u-boot can update the MAC addresses */
|
||||||
|
+ ethernet1 = ð0;
|
||||||
|
+ ethernet2 = ð1;
|
||||||
|
+ ethernet3 = ð2;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ chosen {
|
||||||
|
+ stdout-path = "serial0:115200n8";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ reg_3p3v: regulator-3p3v {
|
||||||
|
+ compatible = "regulator-fixed";
|
||||||
|
+ regulator-name = "3P3V";
|
||||||
|
+ regulator-min-microvolt = <3300000>;
|
||||||
|
+ regulator-max-microvolt = <3300000>;
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ soc {
|
||||||
|
+ internal-regs {
|
||||||
|
+ ethernet@30000 {
|
||||||
|
+ phy-mode = "sgmii";
|
||||||
|
+ status = "okay";
|
||||||
|
+
|
||||||
|
+ fixed-link {
|
||||||
|
+ speed = <1000>;
|
||||||
|
+ full-duplex;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ethernet@34000 {
|
||||||
|
+ phy-mode = "sgmii";
|
||||||
|
+ status = "okay";
|
||||||
|
+
|
||||||
|
+ fixed-link {
|
||||||
|
+ speed = <1000>;
|
||||||
|
+ full-duplex;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ i2c@11000 {
|
||||||
|
+ /* Is there anything on this? */
|
||||||
|
+ clock-frequency = <100000>;
|
||||||
|
+ pinctrl-0 = <&i2c0_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ status = "okay";
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * PCA9655 GPIO expander, up to 1MHz clock.
|
||||||
|
+ * 0-CON3 CLKREQ#
|
||||||
|
+ * 1-CON3 PERST#
|
||||||
|
+ * 2-CON2 PERST#
|
||||||
|
+ * 3-CON3 W_DISABLE
|
||||||
|
+ * 4-CON2 CLKREQ#
|
||||||
|
+ * 5-USB3 overcurrent
|
||||||
|
+ * 6-USB3 power
|
||||||
|
+ * 7-CON2 W_DISABLE
|
||||||
|
+ * 8-JP4 P1
|
||||||
|
+ * 9-JP4 P4
|
||||||
|
+ * 10-JP4 P5
|
||||||
|
+ * 11-m.2 DEVSLP
|
||||||
|
+ * 12-SFP_LOS
|
||||||
|
+ * 13-SFP_TX_FAULT
|
||||||
|
+ * 14-SFP_TX_DISABLE
|
||||||
|
+ * 15-SFP_MOD_DEF0
|
||||||
|
+ */
|
||||||
|
+ expander0: gpio-expander@20 {
|
||||||
|
+ /*
|
||||||
|
+ * This is how it should be:
|
||||||
|
+ * compatible = "onnn,pca9655",
|
||||||
|
+ * "nxp,pca9555";
|
||||||
|
+ * but you can't do this because of
|
||||||
|
+ * the way I2C works.
|
||||||
|
+ */
|
||||||
|
+ compatible = "nxp,pca9555";
|
||||||
|
+ gpio-controller;
|
||||||
|
+ #gpio-cells = <2>;
|
||||||
|
+ reg = <0x20>;
|
||||||
|
+
|
||||||
|
+ pcie1_0_clkreq {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <0 GPIO_ACTIVE_LOW>;
|
||||||
|
+ input;
|
||||||
|
+ line-name = "pcie1.0-clkreq";
|
||||||
|
+ };
|
||||||
|
+ pcie1_0_w_disable {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <3 GPIO_ACTIVE_LOW>;
|
||||||
|
+ output-low;
|
||||||
|
+ line-name = "pcie1.0-w-disable";
|
||||||
|
+ };
|
||||||
|
+ pcie2_0_clkreq {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <4 GPIO_ACTIVE_LOW>;
|
||||||
|
+ input;
|
||||||
|
+ line-name = "pcie2.0-clkreq";
|
||||||
|
+ };
|
||||||
|
+ pcie2_0_w_disable {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <7 GPIO_ACTIVE_LOW>;
|
||||||
|
+ output-low;
|
||||||
|
+ line-name = "pcie2.0-w-disable";
|
||||||
|
+ };
|
||||||
|
+ usb3_ilimit {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <5 GPIO_ACTIVE_LOW>;
|
||||||
|
+ input;
|
||||||
|
+ line-name = "usb3-current-limit";
|
||||||
|
+ };
|
||||||
|
+ usb3_power {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ output-high;
|
||||||
|
+ line-name = "usb3-power";
|
||||||
|
+ };
|
||||||
|
+ m2_devslp {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <11 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ output-low;
|
||||||
|
+ line-name = "m.2 devslp";
|
||||||
|
+ };
|
||||||
|
+ sfp_los {
|
||||||
|
+ /* SFP loss of signal */
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <12 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ input;
|
||||||
|
+ line-name = "sfp-los";
|
||||||
|
+ };
|
||||||
|
+ sfp_tx_fault {
|
||||||
|
+ /* SFP laser fault */
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ input;
|
||||||
|
+ line-name = "sfp-tx-fault";
|
||||||
|
+ };
|
||||||
|
+ sfp_tx_disable {
|
||||||
|
+ /* SFP transmit disable */
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <14 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ output-low;
|
||||||
|
+ line-name = "sfp-tx-disable";
|
||||||
|
+ };
|
||||||
|
+ sfp_mod_def0 {
|
||||||
|
+ /* SFP module present */
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <15 GPIO_ACTIVE_LOW>;
|
||||||
|
+ input;
|
||||||
|
+ line-name = "sfp-mod-def0";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ /* The MCP3021 is 100kHz clock only */
|
||||||
|
+ mikrobus_adc: mcp3021@4c {
|
||||||
|
+ compatible = "microchip,mcp3021";
|
||||||
|
+ reg = <0x4c>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ /* Also something at 0x64 */
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ i2c@11100 {
|
||||||
|
+ /*
|
||||||
|
+ * Routed to SFP, mikrobus, and PCIe.
|
||||||
|
+ * SFP limits this to 100kHz, and requires
|
||||||
|
+ * an AT24C01A/02/04 with address pins tied
|
||||||
|
+ * low, which takes addresses 0x50 and 0x51.
|
||||||
|
+ * Mikrobus doesn't specify beyond an I2C
|
||||||
|
+ * bus being present.
|
||||||
|
+ * PCIe uses ARP to assign addresses, or
|
||||||
|
+ * 0x63-0x64.
|
||||||
|
+ */
|
||||||
|
+ clock-frequency = <100000>;
|
||||||
|
+ pinctrl-0 = <&clearfog_i2c1_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ mdio@72004 {
|
||||||
|
+ pinctrl-0 = <&mdio_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+
|
||||||
|
+ phy_dedicated: ethernet-phy@0 {
|
||||||
|
+ /*
|
||||||
|
+ * Annoyingly, the marvell phy driver
|
||||||
|
+ * configures the LED register, rather
|
||||||
|
+ * than preserving reset-loaded setting.
|
||||||
|
+ * We undo that rubbish here.
|
||||||
|
+ */
|
||||||
|
+ marvell,reg-init = <3 16 0 0x101e>;
|
||||||
|
+ reg = <0>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ pinctrl@18000 {
|
||||||
|
+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
|
||||||
|
+ marvell,pins = "mpp46";
|
||||||
|
+ marvell,function = "ref";
|
||||||
|
+ };
|
||||||
|
+ clearfog_dsa0_pins: clearfog-dsa0-pins {
|
||||||
|
+ marvell,pins = "mpp23", "mpp41";
|
||||||
|
+ marvell,function = "gpio";
|
||||||
|
+ };
|
||||||
|
+ clearfog_i2c1_pins: i2c1-pins {
|
||||||
|
+ /* SFP, PCIe, mSATA, mikrobus */
|
||||||
|
+ marvell,pins = "mpp26", "mpp27";
|
||||||
|
+ marvell,function = "i2c1";
|
||||||
|
+ };
|
||||||
|
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
|
||||||
|
+ marvell,pins = "mpp20";
|
||||||
|
+ marvell,function = "gpio";
|
||||||
|
+ };
|
||||||
|
+ clearfog_sdhci_pins: clearfog-sdhci-pins {
|
||||||
|
+ marvell,pins = "mpp21", "mpp28",
|
||||||
|
+ "mpp37", "mpp38",
|
||||||
|
+ "mpp39", "mpp40";
|
||||||
|
+ marvell,function = "sd0";
|
||||||
|
+ };
|
||||||
|
+ clearfog_spi1_cs_pins: spi1-cs-pins {
|
||||||
|
+ marvell,pins = "mpp55";
|
||||||
|
+ marvell,function = "spi1";
|
||||||
|
+ };
|
||||||
|
+ mikro_pins: mikro-pins {
|
||||||
|
+ /* int: mpp22 rst: mpp29 */
|
||||||
|
+ marvell,pins = "mpp22", "mpp29";
|
||||||
|
+ marvell,function = "gpio";
|
||||||
|
+ };
|
||||||
|
+ mikro_spi_pins: mikro-spi-pins {
|
||||||
|
+ marvell,pins = "mpp43";
|
||||||
|
+ marvell,function = "spi1";
|
||||||
|
+ };
|
||||||
|
+ mikro_uart_pins: mikro-uart-pins {
|
||||||
|
+ marvell,pins = "mpp24", "mpp25";
|
||||||
|
+ marvell,function = "ua1";
|
||||||
|
+ };
|
||||||
|
+ rear_button_pins: rear-button-pins {
|
||||||
|
+ marvell,pins = "mpp34";
|
||||||
|
+ marvell,function = "gpio";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sata@a8000 {
|
||||||
|
+ /* pinctrl? */
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sata@e0000 {
|
||||||
|
+ /* pinctrl? */
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdhci@d8000 {
|
||||||
|
+ bus-width = <4>;
|
||||||
|
+ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
|
||||||
|
+ no-1-8-v;
|
||||||
|
+ pinctrl-0 = <&clearfog_sdhci_pins
|
||||||
|
+ &clearfog_sdhci_cd_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ status = "okay";
|
||||||
|
+ vmmc = <®_3p3v>;
|
||||||
|
+ wp-inverted;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ serial@12100 {
|
||||||
|
+ /* mikrobus uart */
|
||||||
|
+ pinctrl-0 = <&mikro_uart_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ spi@10680 {
|
||||||
|
+ /*
|
||||||
|
+ * We don't seem to have the W25Q32 on the
|
||||||
|
+ * A1 Rev 2.0 boards, so disable SPI.
|
||||||
|
+ * CS0: W25Q32 (doesn't appear to be present)
|
||||||
|
+ * CS1:
|
||||||
|
+ * CS2: mikrobus
|
||||||
|
+ */
|
||||||
|
+ pinctrl-0 = <&spi1_pins
|
||||||
|
+ &clearfog_spi1_cs_pins
|
||||||
|
+ &mikro_spi_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ status = "okay";
|
||||||
|
+
|
||||||
|
+ spi-flash@0 {
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ compatible = "w25q32", "jedec,spi-nor";
|
||||||
|
+ reg = <0>; /* Chip select 0 */
|
||||||
|
+ spi-max-frequency = <3000000>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ usb@58000 {
|
||||||
|
+ /* CON3, nearest power. */
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ usb3@f0000 {
|
||||||
|
+ /* CON2, nearest CPU, USB2 only. */
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ usb3@f8000 {
|
||||||
|
+ /* CON7 */
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ pcie-controller {
|
||||||
|
+ status = "okay";
|
||||||
|
+ /*
|
||||||
|
+ * The two PCIe units are accessible through
|
||||||
|
+ * the mini-PCIe connectors on the board.
|
||||||
|
+ */
|
||||||
|
+ pcie@2,0 {
|
||||||
|
+ /* Port 1, Lane 0. CON3, nearest power. */
|
||||||
|
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+ pcie@3,0 {
|
||||||
|
+ /* Port 2, Lane 0. CON2, nearest CPU. */
|
||||||
|
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ dsa@0 {
|
||||||
|
+ compatible = "marvell,dsa";
|
||||||
|
+ dsa,ethernet = <ð1>;
|
||||||
|
+ dsa,mii-bus = <&mdio>;
|
||||||
|
+ pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+
|
||||||
|
+ switch@0 {
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ reg = <4 0>;
|
||||||
|
+
|
||||||
|
+ port@0 {
|
||||||
|
+ reg = <0>;
|
||||||
|
+ label = "lan1";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@1 {
|
||||||
|
+ reg = <1>;
|
||||||
|
+ label = "lan2";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@2 {
|
||||||
|
+ reg = <2>;
|
||||||
|
+ label = "lan3";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@3 {
|
||||||
|
+ reg = <3>;
|
||||||
|
+ label = "lan4";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@4 {
|
||||||
|
+ reg = <4>;
|
||||||
|
+ label = "lan5";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@5 {
|
||||||
|
+ reg = <5>;
|
||||||
|
+ label = "cpu";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@6 {
|
||||||
|
+ /* 88E1512 external phy */
|
||||||
|
+ reg = <6>;
|
||||||
|
+ label = "lan6";
|
||||||
|
+ fixed-link {
|
||||||
|
+ speed = <1000>;
|
||||||
|
+ full-duplex;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gpio-keys {
|
||||||
|
+ compatible = "gpio-keys";
|
||||||
|
+ pinctrl-0 = <&rear_button_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+
|
||||||
|
+ button_0 {
|
||||||
|
+ /* The rear SW3 button */
|
||||||
|
+ label = "Rear Button";
|
||||||
|
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||||
|
+ linux,can-disable;
|
||||||
|
+ linux,code = <BTN_0>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
|
||||||
|
@@ -0,0 +1,115 @@
|
||||||
|
+/*
|
||||||
|
+ * Device Tree file for SolidRun Armada 38x Microsom
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2015 Russell King
|
||||||
|
+ *
|
||||||
|
+ * This board is in development; the contents of this file work with
|
||||||
|
+ * the A1 rev 2.0 of the board, which does not represent final
|
||||||
|
+ * production board. Things will change, don't expect this file to
|
||||||
|
+ * remain compatible info the future.
|
||||||
|
+ *
|
||||||
|
+ * This file is dual-licensed: you can use it either under the terms
|
||||||
|
+ * of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
+ * licensing only applies to this file, and not this project as a
|
||||||
|
+ * whole.
|
||||||
|
+ *
|
||||||
|
+ * a) This file is free software; you can redistribute it and/or
|
||||||
|
+ * modify it under the terms of the GNU General Public License
|
||||||
|
+ * version 2 as published by the Free Software Foundation.
|
||||||
|
+ *
|
||||||
|
+ * This file is distributed in the hope that it will be useful
|
||||||
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+ * GNU General Public License for more details.
|
||||||
|
+ *
|
||||||
|
+ * Or, alternatively
|
||||||
|
+ *
|
||||||
|
+ * b) Permission is hereby granted, free of charge, to any person
|
||||||
|
+ * obtaining a copy of this software and associated documentation
|
||||||
|
+ * files (the "Software"), to deal in the Software without
|
||||||
|
+ * restriction, including without limitation the rights to use
|
||||||
|
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
+ * sell copies of the Software, and to permit persons to whom the
|
||||||
|
+ * Software is furnished to do so, subject to the following
|
||||||
|
+ * conditions:
|
||||||
|
+ *
|
||||||
|
+ * The above copyright notice and this permission notice shall be
|
||||||
|
+ * included in all copies or substantial portions of the Software.
|
||||||
|
+ *
|
||||||
|
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||||
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||||
|
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
+ * OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
+ */
|
||||||
|
+#include <dt-bindings/input/input.h>
|
||||||
|
+#include <dt-bindings/gpio/gpio.h>
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ memory {
|
||||||
|
+ device_type = "memory";
|
||||||
|
+ reg = <0x00000000 0x10000000>; /* 256 MB */
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ soc {
|
||||||
|
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||||
|
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||||
|
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||||
|
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
|
||||||
|
+
|
||||||
|
+ internal-regs {
|
||||||
|
+ ethernet@70000 {
|
||||||
|
+ pinctrl-0 = <&ge0_rgmii_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ phy = <&phy_dedicated>;
|
||||||
|
+ phy-mode = "rgmii-id";
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ mdio@72004 {
|
||||||
|
+ /*
|
||||||
|
+ * Add the phy clock here, so the phy can be
|
||||||
|
+ * accessed to read its IDs prior to binding
|
||||||
|
+ * with the driver.
|
||||||
|
+ */
|
||||||
|
+ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+
|
||||||
|
+ phy_dedicated: ethernet-phy@0 {
|
||||||
|
+ /*
|
||||||
|
+ * Annoyingly, the marvell phy driver
|
||||||
|
+ * configures the LED register, rather
|
||||||
|
+ * than preserving reset-loaded setting.
|
||||||
|
+ * We undo that rubbish here.
|
||||||
|
+ */
|
||||||
|
+ marvell,reg-init = <3 16 0 0x101e>;
|
||||||
|
+ reg = <0>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ pinctrl@18000 {
|
||||||
|
+ microsom_phy_clk_pins: microsom-phy-clk-pins {
|
||||||
|
+ marvell,pins = "mpp45";
|
||||||
|
+ marvell,function = "ref";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ rtc@a3800 {
|
||||||
|
+ /*
|
||||||
|
+ * If the rtc doesn't work, run "date reset"
|
||||||
|
+ * twice in u-boot.
|
||||||
|
+ */
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ serial@12000 {
|
||||||
|
+ pinctrl-0 = <&uart0_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
@ -0,0 +1,256 @@ |
|||||||
|
From c49e99c2b25a412623412a461bb751239208b9b3 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Marcin Wojtas <mw@semihalf.com>
|
||||||
|
Date: Mon, 14 Mar 2016 09:38:58 +0100
|
||||||
|
Subject: [PATCH] ARM: dts: armada-38x: enable buffer manager support on Armada
|
||||||
|
38x boards
|
||||||
|
|
||||||
|
Since mvneta driver supports using hardware buffer management (BM), in
|
||||||
|
order to use it, board files have to be adjusted accordingly. This commit
|
||||||
|
enables BM on:
|
||||||
|
* A385-DB-AP - each port has its own pool for long and common pool for
|
||||||
|
short packets,
|
||||||
|
* A388-ClearFog - same as above,
|
||||||
|
* A388-DB - to each port unique 'short' and 'long' pools are mapped,
|
||||||
|
* A388-GP - same as above.
|
||||||
|
|
||||||
|
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
|
||||||
|
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
|
||||||
|
|
||||||
|
[gregory.clement@free-electrons.com: add suppport for the ClearFog board]
|
||||||
|
|
||||||
|
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
|
||||||
|
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||||
|
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||||
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/armada-385-db-ap.dts | 20 +++++++++++++++++++-
|
||||||
|
arch/arm/boot/dts/armada-388-clearfog.dts | 6 ++++++
|
||||||
|
arch/arm/boot/dts/armada-388-db.dts | 17 ++++++++++++++++-
|
||||||
|
arch/arm/boot/dts/armada-388-gp.dts | 17 ++++++++++++++++-
|
||||||
|
arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 15 ++++++++++++++-
|
||||||
|
5 files changed, 71 insertions(+), 4 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||||
|
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||||
|
@@ -61,7 +61,8 @@
|
||||||
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||||
|
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||||
|
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||||
|
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
|
||||||
|
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
||||||
|
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||||
|
|
||||||
|
internal-regs {
|
||||||
|
spi1: spi@10680 {
|
||||||
|
@@ -138,12 +139,18 @@
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy2>;
|
||||||
|
phy-mode = "sgmii";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <1>;
|
||||||
|
+ bm,pool-short = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethernet@34000 {
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy1>;
|
||||||
|
phy-mode = "sgmii";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <2>;
|
||||||
|
+ bm,pool-short = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethernet@70000 {
|
||||||
|
@@ -157,6 +164,13 @@
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy0>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <0>;
|
||||||
|
+ bm,pool-short = <3>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ bm@c8000 {
|
||||||
|
+ status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
nfc: flash@d0000 {
|
||||||
|
@@ -178,6 +192,10 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+ bm-bppi {
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
pcie-controller {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||||
|
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||||
|
@@ -78,6 +78,9 @@
|
||||||
|
internal-regs {
|
||||||
|
ethernet@30000 {
|
||||||
|
phy-mode = "sgmii";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <2>;
|
||||||
|
+ bm,pool-short = <1>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
@@ -88,6 +91,9 @@
|
||||||
|
|
||||||
|
ethernet@34000 {
|
||||||
|
phy-mode = "sgmii";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <3>;
|
||||||
|
+ bm,pool-short = <1>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
--- a/arch/arm/boot/dts/armada-388-db.dts
|
||||||
|
+++ b/arch/arm/boot/dts/armada-388-db.dts
|
||||||
|
@@ -66,7 +66,8 @@
|
||||||
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||||
|
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||||
|
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||||
|
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
|
||||||
|
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
||||||
|
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||||
|
|
||||||
|
internal-regs {
|
||||||
|
spi@10600 {
|
||||||
|
@@ -99,6 +100,9 @@
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy1>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <2>;
|
||||||
|
+ bm,pool-short = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@58000 {
|
||||||
|
@@ -109,6 +113,9 @@
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy0>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <0>;
|
||||||
|
+ bm,pool-short = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio@72004 {
|
||||||
|
@@ -129,6 +136,10 @@
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ bm@c8000 {
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
flash@d0000 {
|
||||||
|
status = "okay";
|
||||||
|
num-cs = <1>;
|
||||||
|
@@ -169,6 +180,10 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+ bm-bppi {
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
pcie-controller {
|
||||||
|
status = "okay";
|
||||||
|
/*
|
||||||
|
--- a/arch/arm/boot/dts/armada-388-gp.dts
|
||||||
|
+++ b/arch/arm/boot/dts/armada-388-gp.dts
|
||||||
|
@@ -60,7 +60,8 @@
|
||||||
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||||
|
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||||
|
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||||
|
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
|
||||||
|
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
||||||
|
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||||
|
|
||||||
|
internal-regs {
|
||||||
|
spi@10600 {
|
||||||
|
@@ -133,6 +134,9 @@
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy1>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <2>;
|
||||||
|
+ bm,pool-short = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* CON4 */
|
||||||
|
@@ -152,6 +156,9 @@
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy0>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <0>;
|
||||||
|
+ bm,pool-short = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
@@ -186,6 +193,10 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+ bm@c8000 {
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
sata@e0000 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
|
||||||
|
@@ -240,6 +251,10 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+ bm-bppi {
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
pcie-controller {
|
||||||
|
status = "okay";
|
||||||
|
/*
|
||||||
|
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
|
||||||
|
@@ -58,7 +58,8 @@
|
||||||
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||||
|
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||||
|
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||||
|
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
|
||||||
|
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
||||||
|
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||||
|
|
||||||
|
internal-regs {
|
||||||
|
ethernet@70000 {
|
||||||
|
@@ -66,6 +67,9 @@
|
||||||
|
pinctrl-names = "default";
|
||||||
|
phy = <&phy_dedicated>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
+ buffer-manager = <&bm>;
|
||||||
|
+ bm,pool-long = <0>;
|
||||||
|
+ bm,pool-short = <1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
@@ -110,6 +114,15 @@
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ bm@c8000 {
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ bm-bppi {
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
};
|
||||||
|
};
|
@ -0,0 +1,41 @@ |
|||||||
|
From d261861ab52623e34a25fe6ae76714456edda033 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||||
|
Date: Sun, 10 Jul 2016 16:27:38 +0100
|
||||||
|
Subject: [PATCH] ARM: dts: armada-388-clearfog: remove duplicate mdio entry
|
||||||
|
|
||||||
|
The clearfog DTS should not be defining the on-board phy, this device
|
||||||
|
is located on the microsom. Remove the duplicated definition.
|
||||||
|
|
||||||
|
Reported-by: Jon Nettleton <jon@solid-run.com>
|
||||||
|
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||||
|
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||||
|
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/armada-388-clearfog.dts | 16 ----------------
|
||||||
|
1 file changed, 16 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||||
|
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||||
|
@@ -239,22 +239,6 @@
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
- mdio@72004 {
|
||||||
|
- pinctrl-0 = <&mdio_pins>;
|
||||||
|
- pinctrl-names = "default";
|
||||||
|
-
|
||||||
|
- phy_dedicated: ethernet-phy@0 {
|
||||||
|
- /*
|
||||||
|
- * Annoyingly, the marvell phy driver
|
||||||
|
- * configures the LED register, rather
|
||||||
|
- * than preserving reset-loaded setting.
|
||||||
|
- * We undo that rubbish here.
|
||||||
|
- */
|
||||||
|
- marvell,reg-init = <3 16 0 0x101e>;
|
||||||
|
- reg = <0>;
|
||||||
|
- };
|
||||||
|
- };
|
||||||
|
-
|
||||||
|
pinctrl@18000 {
|
||||||
|
clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
|
||||||
|
marvell,pins = "mpp46";
|
@ -1,10 +0,0 @@ |
|||||||
--- a/arch/arm/boot/dts/Makefile
|
|
||||||
+++ b/arch/arm/boot/dts/Makefile
|
|
||||||
@@ -749,6 +749,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
|
|
||||||
armada-385-linksys-caiman.dtb \
|
|
||||||
armada-385-linksys-cobra.dtb \
|
|
||||||
armada-385-linksys-shelby.dtb \
|
|
||||||
+ armada-388-clearfog.dtb \
|
|
||||||
armada-388-db.dtb \
|
|
||||||
armada-388-gp.dtb \
|
|
||||||
armada-388-rd.dtb
|
|
Loading…
Reference in new issue