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@ -1,16 +1,34 @@ |
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--- a/arch/mips/include/asm/r4kcache.h
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -25,6 +25,20 @@
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@@ -25,6 +25,38 @@
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extern void (*r4k_blast_dcache)(void);
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extern void (*r4k_blast_dcache)(void);
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extern void (*r4k_blast_icache)(void);
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extern void (*r4k_blast_icache)(void);
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+#ifdef CONFIG_BCM47XX
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+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
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+#include <asm/paccess.h>
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+#include <asm/paccess.h>
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+#include <linux/ssb/ssb.h>
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+#include <linux/ssb/ssb.h>
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+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
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+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
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+
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+static inline unsigned long bcm4710_dummy_rreg(void)
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+{
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+ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
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+}
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+
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+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
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+
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+static inline unsigned long bcm4710_fill_tlb(void *addr)
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+{
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+ return *(unsigned long *)addr;
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+}
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+
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+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
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+
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+static inline void bcm4710_protected_fill_tlb(void *addr)
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+{
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+ unsigned long x;
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+ get_dbe(x, (unsigned long *)addr);;
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+}
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+
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+#else
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+#else
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+#define BCM4710_DUMMY_RREG()
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+#define BCM4710_DUMMY_RREG()
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+
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+
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@ -21,7 +39,7 @@ |
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/*
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/*
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* This macro return a properly sign-extended address suitable as base address
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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* for indexed cache operations. Two issues here:
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@@ -98,6 +112,7 @@ static inline void flush_icache_line_ind
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@@ -98,6 +130,7 @@ static inline void flush_icache_line_ind
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static inline void flush_dcache_line_indexed(unsigned long addr)
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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{
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__dflush_prologue
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__dflush_prologue
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@ -29,7 +47,7 @@ |
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cache_op(Index_Writeback_Inv_D, addr);
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cache_op(Index_Writeback_Inv_D, addr);
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__dflush_epilogue
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__dflush_epilogue
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}
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}
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@@ -125,6 +140,7 @@ static inline void flush_icache_line(uns
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@@ -125,6 +158,7 @@ static inline void flush_icache_line(uns
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static inline void flush_dcache_line(unsigned long addr)
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static inline void flush_dcache_line(unsigned long addr)
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{
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{
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__dflush_prologue
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__dflush_prologue
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@ -37,7 +55,7 @@ |
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cache_op(Hit_Writeback_Inv_D, addr);
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cache_op(Hit_Writeback_Inv_D, addr);
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__dflush_epilogue
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__dflush_epilogue
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}
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}
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@@ -132,6 +148,7 @@ static inline void flush_dcache_line(uns
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@@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns
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static inline void invalidate_dcache_line(unsigned long addr)
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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{
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__dflush_prologue
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__dflush_prologue
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@ -45,7 +63,7 @@ |
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cache_op(Hit_Invalidate_D, addr);
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cache_op(Hit_Invalidate_D, addr);
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__dflush_epilogue
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__dflush_epilogue
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}
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}
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@@ -187,6 +204,7 @@ static inline void protected_flush_icach
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@@ -187,6 +222,7 @@ static inline void protected_flush_icach
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#ifdef CONFIG_EVA
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#ifdef CONFIG_EVA
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protected_cachee_op(Hit_Invalidate_I, addr);
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protected_cachee_op(Hit_Invalidate_I, addr);
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#else
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#else
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@ -53,7 +71,7 @@ |
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protected_cache_op(Hit_Invalidate_I, addr);
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protected_cache_op(Hit_Invalidate_I, addr);
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#endif
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#endif
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break;
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break;
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@@ -201,6 +219,7 @@ static inline void protected_flush_icach
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@@ -201,6 +237,7 @@ static inline void protected_flush_icach
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*/
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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{
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@ -61,7 +79,7 @@ |
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#ifdef CONFIG_EVA
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#ifdef CONFIG_EVA
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protected_cachee_op(Hit_Writeback_Inv_D, addr);
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protected_cachee_op(Hit_Writeback_Inv_D, addr);
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#else
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#else
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@@ -554,8 +573,51 @@ static inline void invalidate_tcache_pag
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@@ -554,8 +591,51 @@ static inline void invalidate_tcache_pag
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: "r" (base), \
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: "r" (base), \
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"i" (op));
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"i" (op));
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@ -114,7 +132,7 @@ |
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static inline void extra##blast_##pfx##cache##lsize(void) \
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static inline void extra##blast_##pfx##cache##lsize(void) \
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{ \
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{ \
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unsigned long start = INDEX_BASE; \
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unsigned long start = INDEX_BASE; \
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@@ -567,6 +629,7 @@ static inline void extra##blast_##pfx##c
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@@ -567,6 +647,7 @@ static inline void extra##blast_##pfx##c
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\
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\
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__##pfx##flush_prologue \
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__##pfx##flush_prologue \
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\
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\
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@ -122,7 +140,7 @@ |
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws, indexop); \
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cache##lsize##_unroll32(addr|ws, indexop); \
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@@ -581,6 +644,7 @@ static inline void extra##blast_##pfx##c
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@@ -581,6 +662,7 @@ static inline void extra##blast_##pfx##c
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\
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\
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__##pfx##flush_prologue \
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__##pfx##flush_prologue \
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\
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\
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@ -130,7 +148,7 @@ |
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do { \
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do { \
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cache##lsize##_unroll32(start, hitop); \
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cache##lsize##_unroll32(start, hitop); \
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start += lsize * 32; \
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start += lsize * 32; \
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@@ -599,6 +663,8 @@ static inline void extra##blast_##pfx##c
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@@ -599,6 +681,8 @@ static inline void extra##blast_##pfx##c
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current_cpu_data.desc.waybit; \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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unsigned long ws, addr; \
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\
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\
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@ -139,7 +157,7 @@ |
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__##pfx##flush_prologue \
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__##pfx##flush_prologue \
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\
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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@@ -608,26 +674,26 @@ static inline void extra##blast_##pfx##c
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@@ -608,26 +692,26 @@ static inline void extra##blast_##pfx##c
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__##pfx##flush_epilogue \
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__##pfx##flush_epilogue \
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}
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}
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@ -156,13 +174,6 @@ |
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
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-
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-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
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-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
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@ -176,7 +187,13 @@ |
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
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+
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-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
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-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
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+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
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+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
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+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
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+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
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+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
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+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
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@ -186,7 +203,7 @@ |
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#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
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#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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@@ -656,17 +722,19 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
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@@ -656,17 +740,19 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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/* build blast_xxx_range, protected_blast_xxx_range */
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/* build blast_xxx_range, protected_blast_xxx_range */
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@ -207,7 +224,7 @@ |
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prot##cache_op(hitop, addr); \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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if (addr == aend) \
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break; \
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break; \
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@@ -678,8 +746,8 @@ static inline void prot##extra##blast_##
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@@ -678,8 +764,8 @@ static inline void prot##extra##blast_##
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#ifndef CONFIG_EVA
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#ifndef CONFIG_EVA
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@ -218,7 +235,7 @@ |
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#else
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#else
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@@ -716,14 +784,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
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@@ -716,14 +802,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
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__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
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__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
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#endif
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#endif
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@ -255,17 +272,46 @@ |
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.endm
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.endm
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--- a/arch/mips/kernel/genex.S
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--- a/arch/mips/kernel/genex.S
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+++ b/arch/mips/kernel/genex.S
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+++ b/arch/mips/kernel/genex.S
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@@ -32,6 +32,10 @@
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@@ -21,6 +21,19 @@
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#include <asm/war.h>
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#include <asm/thread_info.h>
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+#ifdef CONFIG_BCM47XX
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+# ifdef eret
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+# undef eret
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+# endif
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+# define eret \
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+ .set push; \
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+ .set noreorder; \
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+ nop; \
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+ nop; \
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+ eret; \
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+ .set pop;
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+#endif
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+
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__INIT
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/*
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@@ -32,6 +45,9 @@
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NESTED(except_vec3_generic, 0, sp)
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NESTED(except_vec3_generic, 0, sp)
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.set push
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.set push
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.set noat
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.set noat
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+#ifdef CONFIG_BCM47XX
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+#ifdef CONFIG_BCM47XX
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+ nop
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+ nop
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+ nop
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+#endif
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+#endif
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#if R5432_CP0_INTERRUPT_WAR
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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mfc0 k0, CP0_INDEX
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#endif
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#endif
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@@ -55,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp)
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.set push
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.set arch=r4000
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.set noat
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+#ifdef CONFIG_BCM47XX
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+ nop
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+#endif
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mfc0 k1, CP0_CAUSE
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li k0, 31<<2
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andi k1, k1, 0x7c
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--- a/arch/mips/mm/c-r4k.c
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -39,6 +39,9 @@
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@@ -39,6 +39,9 @@
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@ -273,7 +319,7 @@ |
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#include <asm/mips-cm.h>
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#include <asm/mips-cm.h>
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+/* For enabling BCM4710 cache workarounds */
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+/* For enabling BCM4710 cache workarounds */
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+int bcm4710 = 0;
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+static int bcm4710 = 0;
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+
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+
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/*
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/*
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* Bits describing what cache ops an IPI callback function may perform.
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* Bits describing what cache ops an IPI callback function may perform.
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@ -340,7 +386,7 @@ |
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struct cpuinfo_mips *c = ¤t_cpu_data;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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+ /* Check if special workarounds are required */
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM47XX
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+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
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+ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ bcm4710 = 1;
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@ -369,23 +415,53 @@ |
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/*
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/*
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--- a/arch/mips/mm/tlbex.c
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -1281,6 +1281,9 @@ static void build_r4000_tlb_refill_handl
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@@ -943,6 +943,9 @@ build_get_pgde32(u32 **p, unsigned int t
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/* No need for uasm_i_nop */
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uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
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}
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uasm_i_addu(p, ptr, tmp, ptr);
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#else
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+#ifdef CONFIG_BCM47XX
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(&p);
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+ uasm_i_nop(p);
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+#endif
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+#endif
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UASM_i_LA_mostly(p, ptr, pgdc);
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#endif
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uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
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@@ -1284,6 +1287,9 @@ static void build_r4000_tlb_refill_handl
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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#else
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#else
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@@ -1868,6 +1871,9 @@ build_r4000_tlbchange_handler_head(u32 *
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+# ifdef CONFIG_BCM47XX
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{
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+ uasm_i_nop(&p);
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struct work_registers wr = build_get_work_registers(p);
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+# endif
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build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
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#endif
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@@ -1295,6 +1301,9 @@ static void build_r4000_tlb_refill_handl
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build_update_entries(&p, K0, K1);
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build_tlb_write_entry(&p, &l, &r, tlb_random);
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uasm_l_leave(&l, p);
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+#ifdef CONFIG_BCM47XX
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(p);
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+ uasm_i_nop(&p);
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+#endif
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+#endif
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uasm_i_eret(&p); /* return from trap */
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}
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#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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@@ -1871,6 +1880,9 @@ build_r4000_tlbchange_handler_head(u32 *
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
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build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
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#else
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#else
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+# ifdef CONFIG_BCM47XX
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+ uasm_i_nop(p);
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+# endif
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build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
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#endif
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@@ -1917,6 +1929,9 @@ build_r4000_tlbchange_handler_tail(u32 *
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build_tlb_write_entry(p, l, r, tlb_indexed);
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uasm_l_leave(l, *p);
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build_restore_work_registers(p);
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(p);
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+#endif
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uasm_i_eret(p); /* return from trap */
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#ifdef CONFIG_64BIT
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