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@ -26,141 +26,142 @@ |
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#define NUM_RX_DESC 256 |
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#define NUM_TX_DESC 256 |
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#define RAMIPS_DELAY_EN_INT 0x80 |
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#define RAMIPS_DELAY_MAX_INT 0x04 |
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#define RAMIPS_DELAY_MAX_TOUT 0x04 |
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#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT) |
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#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN) |
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#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000 |
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/* interrupt bitd */ |
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#define RAMIPS_CNT_PPE_AF BIT(31) |
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#define RAMIPS_CNT_GDM_AF BIT(29) |
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#define RAMIPS_PSE_P2_FC BIT(26) |
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#define RAMIPS_PSE_BUF_DROP BIT(24) |
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#define RAMIPS_GDM_OTHER_DROP BIT(23) |
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#define RAMIPS_PSE_P1_FC BIT(22) |
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#define RAMIPS_PSE_P0_FC BIT(21) |
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#define RAMIPS_PSE_FQ_EMPTY BIT(20) |
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#define RAMIPS_GE1_STA_CHG BIT(18) |
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#define RAMIPS_TX_COHERENT BIT(17) |
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#define RAMIPS_RX_COHERENT BIT(16) |
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#define RAMIPS_TX_DONE_INT3 BIT(11) |
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#define RAMIPS_TX_DONE_INT2 BIT(10) |
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#define RAMIPS_TX_DONE_INT1 BIT(9) |
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#define RAMIPS_TX_DONE_INT0 BIT(8) |
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#define RAMIPS_RX_DONE_INT0 BIT(2) |
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#define RAMIPS_TX_DLY_INT BIT(1) |
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#define RAMIPS_RX_DLY_INT BIT(0) |
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#define RAMIPS_DELAY_EN_INT 0x80 |
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#define RAMIPS_DELAY_MAX_INT 0x04 |
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#define RAMIPS_DELAY_MAX_TOUT 0x04 |
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#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT) |
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#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN) |
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#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000 |
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/* interrupt bits */ |
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#define RAMIPS_CNT_PPE_AF BIT(31) |
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#define RAMIPS_CNT_GDM_AF BIT(29) |
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#define RAMIPS_PSE_P2_FC BIT(26) |
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#define RAMIPS_PSE_BUF_DROP BIT(24) |
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#define RAMIPS_GDM_OTHER_DROP BIT(23) |
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#define RAMIPS_PSE_P1_FC BIT(22) |
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#define RAMIPS_PSE_P0_FC BIT(21) |
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#define RAMIPS_PSE_FQ_EMPTY BIT(20) |
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#define RAMIPS_GE1_STA_CHG BIT(18) |
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#define RAMIPS_TX_COHERENT BIT(17) |
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#define RAMIPS_RX_COHERENT BIT(16) |
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#define RAMIPS_TX_DONE_INT3 BIT(11) |
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#define RAMIPS_TX_DONE_INT2 BIT(10) |
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#define RAMIPS_TX_DONE_INT1 BIT(9) |
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#define RAMIPS_TX_DONE_INT0 BIT(8) |
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#define RAMIPS_RX_DONE_INT0 BIT(2) |
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#define RAMIPS_TX_DLY_INT BIT(1) |
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#define RAMIPS_RX_DLY_INT BIT(0) |
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/* registers */ |
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#define RAMIPS_FE_OFFSET 0x0000 |
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#define RAMIPS_GDMA_OFFSET 0x0020 |
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#define RAMIPS_PSE_OFFSET 0x0040 |
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#define RAMIPS_GDMA2_OFFSET 0x0060 |
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#define RAMIPS_CDMA_OFFSET 0x0080 |
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#define RAMIPS_PDMA_OFFSET 0x0100 |
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#define RAMIPS_PPE_OFFSET 0x0200 |
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#define RAMIPS_CMTABLE_OFFSET 0x0400 |
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#define RAMIPS_POLICYTABLE_OFFSET 0x1000 |
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#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00) |
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#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04) |
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#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08) |
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#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C) |
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#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10) |
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#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14) |
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#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18) |
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#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C) |
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#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00) |
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#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04) |
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#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08) |
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#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C) |
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#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10) |
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#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00) |
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#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04) |
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#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08) |
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#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C) |
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#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10) |
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#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00) |
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#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04) |
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#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08) |
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#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C) |
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#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00) |
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#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04) |
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#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00) |
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#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04) |
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#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08) |
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#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C) |
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#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10) |
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#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14) |
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#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18) |
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#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C) |
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#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20) |
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#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24) |
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#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28) |
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#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C) |
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#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40) |
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#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44) |
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#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48) |
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#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C) |
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#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50) |
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#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54) |
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#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58) |
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#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C) |
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#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30) |
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#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34) |
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#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38) |
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#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C) |
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#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x40) |
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#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x44) |
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#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x48) |
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#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x4C) |
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#define RAMIPS_FE_OFFSET 0x0000 |
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#define RAMIPS_GDMA_OFFSET 0x0020 |
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#define RAMIPS_PSE_OFFSET 0x0040 |
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#define RAMIPS_GDMA2_OFFSET 0x0060 |
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#define RAMIPS_CDMA_OFFSET 0x0080 |
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#define RAMIPS_PDMA_OFFSET 0x0100 |
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#define RAMIPS_PPE_OFFSET 0x0200 |
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#define RAMIPS_CMTABLE_OFFSET 0x0400 |
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#define RAMIPS_POLICYTABLE_OFFSET 0x1000 |
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#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00) |
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#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04) |
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#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08) |
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#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C) |
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#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10) |
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#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14) |
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#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18) |
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#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C) |
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#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00) |
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#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04) |
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#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08) |
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#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C) |
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#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10) |
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#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00) |
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#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04) |
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#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08) |
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#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C) |
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#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10) |
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#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00) |
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#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04) |
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#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08) |
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#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C) |
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#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00) |
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#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04) |
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#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00) |
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#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04) |
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#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08) |
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#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C) |
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#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10) |
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#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14) |
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#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18) |
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#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C) |
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#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20) |
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#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24) |
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#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28) |
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#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C) |
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#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40) |
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#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44) |
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#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48) |
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#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C) |
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#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50) |
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#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54) |
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#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58) |
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#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C) |
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#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30) |
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#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34) |
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#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38) |
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#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C) |
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#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x40) |
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#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x44) |
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#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x48) |
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#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x4C) |
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/* uni-cast port */ |
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#define RAMIPS_GDM1_ICS_EN (0x1 << 22) |
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#define RAMIPS_GDM1_TCS_EN (0x1 << 21) |
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#define RAMIPS_GDM1_UCS_EN (0x1 << 20) |
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#define RAMIPS_GDM1_JMB_EN (0x1 << 19) |
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#define RAMIPS_GDM1_STRPCRC (0x1 << 16) |
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#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12) |
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#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12) |
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#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12) |
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#define RAMIPS_GDM1_ICS_EN BIT(22) |
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#define RAMIPS_GDM1_TCS_EN BIT(21) |
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#define RAMIPS_GDM1_UCS_EN BIT(20) |
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#define RAMIPS_GDM1_JMB_EN BIT(19) |
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#define RAMIPS_GDM1_STRPCRC BIT(16) |
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#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12) |
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#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12) |
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#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12) |
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/* checksums */ |
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#define RAMIPS_ICS_GEN_EN BIT(2) |
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#define RAMIPS_UCS_GEN_EN BIT(1) |
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#define RAMIPS_TCS_GEN_EN BIT(0) |
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/* dma rimg */ |
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#define RAMIPS_PST_DRX_IDX0 BIT(16) |
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#define RAMIPS_PST_DTX_IDX3 BIT(3) |
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#define RAMIPS_PST_DTX_IDX2 BIT(2) |
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#define RAMIPS_PST_DTX_IDX1 BIT(1) |
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#define RAMIPS_PST_DTX_IDX0 BIT(0) |
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#define RAMIPS_TX_WB_DDONE BIT(6) |
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#define RAMIPS_RX_DMA_BUSY BIT(3) |
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#define RAMIPS_TX_DMA_BUSY BIT(1) |
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#define RAMIPS_RX_DMA_EN BIT(2) |
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#define RAMIPS_TX_DMA_EN BIT(0) |
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#define RAMIPS_PDMA_SIZE_4DWORDS (0<<4) |
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#define RAMIPS_PDMA_SIZE_8DWORDS (1<<4) |
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#define RAMIPS_PDMA_SIZE_16DWORDS (2<<4) |
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#define RAMIPS_US_CYC_CNT_MASK 0xff |
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#define RAMIPS_US_CYC_CNT_SHIFT 0x8 |
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#define RAMIPS_US_CYC_CNT_DIVISOR 1000000 |
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#define RX_DMA_PLEN0(x) ((x >> 16) & 0x3fff) |
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#define RX_DMA_LSO BIT(30) |
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#define RX_DMA_DONE BIT(31) |
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#define RAMIPS_ICS_GEN_EN BIT(2) |
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#define RAMIPS_UCS_GEN_EN BIT(1) |
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#define RAMIPS_TCS_GEN_EN BIT(0) |
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/* dma ring */ |
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#define RAMIPS_PST_DRX_IDX0 BIT(16) |
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#define RAMIPS_PST_DTX_IDX3 BIT(3) |
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#define RAMIPS_PST_DTX_IDX2 BIT(2) |
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#define RAMIPS_PST_DTX_IDX1 BIT(1) |
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#define RAMIPS_PST_DTX_IDX0 BIT(0) |
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#define RAMIPS_TX_WB_DDONE BIT(6) |
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#define RAMIPS_RX_DMA_BUSY BIT(3) |
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#define RAMIPS_TX_DMA_BUSY BIT(1) |
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#define RAMIPS_RX_DMA_EN BIT(2) |
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#define RAMIPS_TX_DMA_EN BIT(0) |
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#define RAMIPS_PDMA_SIZE_4DWORDS (0 << 4) |
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#define RAMIPS_PDMA_SIZE_8DWORDS (1 << 4) |
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#define RAMIPS_PDMA_SIZE_16DWORDS (2 << 4) |
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#define RAMIPS_US_CYC_CNT_MASK 0xff |
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#define RAMIPS_US_CYC_CNT_SHIFT 0x8 |
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#define RAMIPS_US_CYC_CNT_DIVISOR 1000000 |
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#define RX_DMA_PLEN0(x) ((x >> 16) & 0x3fff) |
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#define RX_DMA_LSO BIT(30) |
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#define RX_DMA_DONE BIT(31) |
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struct ramips_rx_dma { |
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unsigned int rxd1; |
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unsigned int rxd2; |
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@ -168,14 +169,15 @@ struct ramips_rx_dma { |
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unsigned int rxd4; |
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}; |
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#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) |
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#define TX_DMA_PLEN0(x) ((x & 0x3fff) << 16) |
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#define TX_DMA_LSO BIT(30) |
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#define TX_DMA_DONE BIT(31) |
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#define TX_DMA_QN(x) (x << 16) |
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#define TX_DMA_PN(x) (x << 24) |
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#define TX_DMA_QN_MASK TX_DMA_QN(0x7) |
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#define TX_DMA_PN_MASK TX_DMA_PN(0x7) |
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#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) |
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#define TX_DMA_PLEN0(x) ((x & 0x3fff) << 16) |
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#define TX_DMA_LSO BIT(30) |
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#define TX_DMA_DONE BIT(31) |
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#define TX_DMA_QN(x) (x << 16) |
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#define TX_DMA_PN(x) (x << 24) |
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#define TX_DMA_QN_MASK TX_DMA_QN(0x7) |
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#define TX_DMA_PN_MASK TX_DMA_PN(0x7) |
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struct ramips_tx_dma { |
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unsigned int txd1; |
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unsigned int txd2; |
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@ -185,20 +187,20 @@ struct ramips_tx_dma { |
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struct raeth_priv |
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{ |
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unsigned int phy_rx; |
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unsigned int phy_rx; |
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struct tasklet_struct rx_tasklet; |
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struct ramips_rx_dma *rx; |
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struct sk_buff *rx_skb[NUM_RX_DESC]; |
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struct sk_buff *rx_skb[NUM_RX_DESC]; |
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unsigned int phy_tx; |
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unsigned int phy_tx; |
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struct tasklet_struct tx_housekeeping_tasklet; |
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struct ramips_tx_dma *tx; |
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struct sk_buff *tx_skb[NUM_RX_DESC]; |
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struct sk_buff *tx_skb[NUM_RX_DESC]; |
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unsigned int skb_free_idx; |
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unsigned int skb_free_idx; |
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spinlock_t page_lock; |
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spinlock_t page_lock; |
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struct ramips_eth_platform_data *plat; |
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}; |
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#endif |
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#endif /* RAMIPS_ETH_H */ |
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