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@ -68,7 +68,15 @@ |
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#define AR933X_PLL_CPU_CONFIG_REG 0x00
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#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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@@ -285,7 +305,11 @@
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@@ -165,6 +185,7 @@
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#define AR934X_PLL_CPU_CONFIG_REG 0x00
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#define AR934X_PLL_DDR_CONFIG_REG 0x04
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
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+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
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#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@@ -285,7 +306,11 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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@ -80,7 +88,7 @@ |
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#define AR933X_RESET_USB_HOST BIT(5)
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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@@ -323,6 +347,8 @@
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@@ -323,6 +348,8 @@
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#define AR934X_RESET_MBOX BIT(1)
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#define AR934X_RESET_I2S BIT(0)
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@ -89,7 +97,7 @@ |
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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@@ -427,6 +453,14 @@
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@@ -427,6 +454,14 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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@ -104,7 +112,7 @@ |
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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@@ -434,4 +468,124 @@
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@@ -434,4 +469,124 @@
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#define AR933X_GPIO_COUNT 30
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#define AR934X_GPIO_COUNT 23
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