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@ -72,7 +72,7 @@ |
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#define MT7621_FE_GDM1_AF BIT(28) |
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#define MT7621_FE_GDM1_AF BIT(28) |
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#define MT7621_FE_GDM2_AF BIT(29) |
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#define MT7621_FE_GDM2_AF BIT(29) |
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static const u32 mt7620_reg_table[FE_REG_COUNT] = { |
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static const u16 mt7620_reg_table[FE_REG_COUNT] = { |
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[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, |
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[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, |
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[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, |
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[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, |
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[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, |
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[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, |
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@ -92,7 +92,7 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = { |
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[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2, |
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[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2, |
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}; |
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}; |
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static const u32 mt7621_reg_table[FE_REG_COUNT] = { |
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static const u16 mt7621_reg_table[FE_REG_COUNT] = { |
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[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, |
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[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, |
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[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, |
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[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, |
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[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, |
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[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, |
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