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@ -53,6 +53,8 @@ |
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#define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value |
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#define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) |
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#define TANTOS_CHIP_ID 0x2599 |
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typedef struct |
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{ |
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union |
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@ -115,6 +117,7 @@ static void danube_dma_init(void); |
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int danube_switch_initialize(bd_t * bis) |
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{ |
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struct eth_device *dev; |
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unsigned short chipid; |
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#if 0 |
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printf("Entered danube_switch_initialize()\n"); |
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@ -160,9 +163,13 @@ int danube_switch_initialize(bd_t * bis) |
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eth_register(dev); |
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#if 0 |
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printf("Leaving danube_switch_initialize()\n"); |
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#endif |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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*DANUBE_PPE_ETOP_MDIO_ACC =0xc1010000; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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chipid = (unsigned short)(*DANUBE_PPE_ETOP_MDIO_ACC & 0xffff); |
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if (chipid != TANTOS_CHIP_ID) // not tantos switch.
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{ |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F; |
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while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000); |
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@ -183,6 +190,49 @@ int danube_switch_initialize(bd_t * bis) |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80334000; |
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#endif |
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} |
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else // Tantos switch chip
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{ |
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//printf("Tantos Switch detected!!\n\r");
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80a10004; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80c10004; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80f50773; |
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/* Software workaround. */ |
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/* PHY reset from P0 to P4. */ |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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mdelay(1); |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x81218000; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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mdelay(1); |
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/* P0 */ |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x81200400; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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mdelay(1); |
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/* P1 */ |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x81200420; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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mdelay(1); |
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/* P2 */ |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x81200440; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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mdelay(1); |
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/* P3 */ |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x81200460; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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mdelay(1); |
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/* p4 */ |
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*DANUBE_PPE_ETOP_MDIO_ACC =0x81200480; |
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); |
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mdelay(1); |
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} |
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return 1; |
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} |
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@ -194,8 +244,7 @@ int danube_switch_init(struct eth_device *dev, bd_t * bis) |
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tx_num=0; |
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rx_num=0; |
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/* Reset DMA
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*/ |
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/* Reset DMA */ |
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// serial_puts("i \n\0");
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*DANUBE_DMA_CS=RX_CHAN_NO; |
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@ -299,12 +348,9 @@ Done: |
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int danube_switch_recv(struct eth_device *dev) |
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{ |
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int length = 0; |
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danube_rx_descriptor_t * rx_desc; |
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int anchor_num=0; |
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int i; |
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for (;;) |
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{ |
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rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]); |
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@ -314,7 +360,6 @@ int danube_switch_recv(struct eth_device *dev) |
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break; |
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} |
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length = rx_desc->status.field.DataLen; |
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if (length) |
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{ |
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@ -342,10 +387,8 @@ int danube_switch_recv(struct eth_device *dev) |
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static void danube_init_switch_chip(int mode) |
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{ |
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int i; |
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/*get and set mac address for MAC*/ |
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static unsigned char addr[6]; |
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char *tmp,*end;
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char *tmp; |
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tmp = getenv ("ethaddr"); |
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if (NULL == tmp) { |
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printf("Can't get environment ethaddr!!!\n"); |
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@ -375,17 +418,14 @@ static void danube_init_switch_chip(int mode) |
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static void danube_dma_init(void) |
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{ |
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int i; |
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// serial_puts("d \n\0");
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*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/ |
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/* Reset DMA
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*/ |
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/* Reset DMA */ |
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*DANUBE_DMA_CTRL|=1; |
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*DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/ |
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/* Clear Interrupt Status Register
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*/ |
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/* Clear Interrupt Status Register */ |
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*DANUBE_DMA_IRNCR=0xfffff; |
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/*disable all the dma interrupts*/ |
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*DANUBE_DMA_IRNEN=0; |
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@ -416,8 +456,4 @@ static void danube_dma_init(void) |
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return; |
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} |
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#endif |
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