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@ -151,18 +151,39 @@ enum bcm63xx_regs_set { |
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/*
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* 6345 register sets base address |
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*/ |
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#define BCM_6345_DSL_LMEM_BASE (0xfff00000) |
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#define BCM_6345_PERF_BASE (0xfffe0000) |
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#define BCM_6345_BB_BASE (0xfffe0100) |
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#define BCM_6345_TIMER_BASE (0xfffe0200) |
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#define BCM_6345_WDT_BASE (0xfffe021c) |
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#define BCM_6345_UART0_BASE (0xfffe0300) |
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#define BCM_6345_GPIO_BASE (0xfffe0400) |
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#define BCM_6345_SPI_BASE (0xdeadbeef) |
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#define BCM_6345_UDC0_BASE (0xdeadbeef) |
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#define BCM_6345_USBDMA_BASE (0xfffe2800) |
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#define BCM_6345_ENET0_BASE (0xfffe1800) |
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#define BCM_6345_ENETDMA_BASE (0xfffe2800) |
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#define BCM_6345_PCMCIA_BASE (0xfffe2028) |
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#define BCM_6345_MPI_BASE (0xdeadbeef) |
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#define BCM_6345_OHCI0_BASE (0xfffe2100) |
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) |
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) |
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#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) |
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#define BCM_6345_DSL_BASE (0xdeadbeef) |
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#define BCM_6345_SAR_BASE (0xdeadbeef) |
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#define BCM_6345_UBUS_BASE (0xdeadbeef) |
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#define BCM_6345_ENET1_BASE (0xdeadbeef) |
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#define BCM_6345_EHCI0_BASE (0xdeadbeef) |
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#define BCM_6345_SDRAM_BASE (0xfffe2300) |
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#define BCM_6345_MEMC_BASE (0xdeadbeef) |
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#define BCM_6345_DDR_BASE (0xdeadbeef) |
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/*
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* 6348 register sets base address |
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*/ |
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#define BCM_6348_DSL_LMEM_BASE (0xfff00000) |
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#define BCM_6348_PERF_BASE (0xfffe0000) |
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#define BCM_6348_BB_BASE (0xfffe0100) /* bus bridge registers */ |
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#define BCM_6348_BB_BASE (0xfffe0100) |
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#define BCM_6348_TIMER_BASE (0xfffe0200) |
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#define BCM_6348_WDT_BASE (0xfffe021c) |
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#define BCM_6348_UART0_BASE (0xfffe0300) |
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@ -269,6 +290,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) |
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#endif |
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#ifdef CONFIG_BCM63XX_CPU_6345 |
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switch (set) { |
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case RSET_DSL_LMEM: |
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return BCM_6345_DSL_LMEM_BASE; |
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case RSET_PERF: |
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return BCM_6345_PERF_BASE; |
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case RSET_TIMER: |
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@ -279,6 +302,34 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) |
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return BCM_6345_UART0_BASE; |
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case RSET_GPIO: |
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return BCM_6345_GPIO_BASE; |
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case RSET_SPI_BASE: |
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return BCM_6345_SPI_BASE; |
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case RSET_UDC0: |
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return BCM_6345_UDC0_BASE; |
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case RSET_OHCI0: |
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return BCM_6345_OHCI0_BASE; |
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case RSET_OHCI_PRIV: |
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return BCM_6345_OHCI_PRIV_BASE; |
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case RSET_USBH_PRIV: |
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return BCM_6345_USBH_PRIV_BASE; |
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case RSET_MPI: |
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return BCM_6345_MPI_BASE; |
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case RSET_PCMCIA: |
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return BCM_6345_PCMCIA_BASE; |
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case RSET_DSL: |
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return BCM_6345_DSL_BASE; |
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case RSET_ENET0: |
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return BCM_6345_ENET0_BASE; |
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case RSET_ENETDMA: |
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return BCM_6345_ENETDMA_BASE; |
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case RSET_EHCI0: |
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return BCM_6345_EHCI0_BASE; |
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case RSET_SDRAM: |
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return BCM_6345_SDRAM_BASE; |
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case RSET_MEMC: |
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return BCM_6345_MEMC_BASE; |
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case RSET_DDR: |
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return BCM_6345_DDR_BASE; |
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} |
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#endif |
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#ifdef CONFIG_BCM63XX_CPU_6348 |
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@ -548,6 +599,8 @@ enum bcm63xx_irq { |
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#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) |
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#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
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#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) |
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#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) |
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#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) |
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/*
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* 6348 irqs |
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