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@ -40,6 +40,14 @@ |
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#define BOOT_PLL_ASYNC_MODE 0x02000000 |
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#define BOOT_PLL_2TO1_MODE 0x00008000 |
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#define TNETD7200_CLOCK_ID_CPU 0 |
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#define TNETD7200_CLOCK_ID_DSP 1 |
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#define TNETD7200_CLOCK_ID_USB 2 |
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#define TNETD7200_DEF_CPU_CLK 211000000 |
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#define TNETD7200_DEF_DSP_CLK 125000000 |
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#define TNETD7200_DEF_USB_CLK 48000000 |
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struct tnetd7300_clock { |
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volatile u32 ctrl; |
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#define PREDIV_MASK 0x001f0000 |
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@ -70,18 +78,19 @@ struct tnetd7200_clock { |
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volatile u32 mul; |
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volatile u32 prediv; |
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volatile u32 postdiv; |
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u32 unused2[7]; |
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volatile u32 postdiv2; |
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u32 unused2[6]; |
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volatile u32 cmd; |
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volatile u32 status; |
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volatile u32 cmden; |
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u32 padding[15]; |
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}; |
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} __attribute__ ((packed)); |
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struct tnetd7200_clocks { |
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struct tnetd7200_clock cpu; |
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struct tnetd7200_clock dsp; |
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struct tnetd7200_clock usb; |
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}; |
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} __attribute__ ((packed)); |
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int ar7_afe_clock = 35328000; |
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int ar7_ref_clock = 25000000; |
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@ -289,55 +298,155 @@ static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock, |
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return base * ((clock->mul & 0xf) + 1) / divisor; |
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} |
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static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, |
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u32 *bootcr, u32 frequency)
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int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
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{ |
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u32 status; |
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int prediv, postdiv, mul; |
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calculate(base, frequency, &prediv, &postdiv, &mul); |
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printk("Clocks: base = %d, frequency = %u, prediv = %d, postdiv = %d, postdiv2 = %d, mul = %d\n", |
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base, frequency, prediv, postdiv, postdiv2, mul); |
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clock->ctrl = 0; |
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clock->prediv = DIVISOR_ENABLE_MASK | prediv; |
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clock->mul = mul; |
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mdelay(1); |
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do { |
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status = clock->status; |
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} while (status & PLL_STATUS); |
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clock->postdiv = DIVISOR_ENABLE_MASK | postdiv; |
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clock->cmden = 1; |
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clock->cmd = 1; |
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do { |
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status = clock->status; |
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} while (status & PLL_STATUS); |
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clock->ctrl = 1; |
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clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F); |
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clock->mul = ((mul - 1) & 0xF); |
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for(mul = 0; mul < 2000; mul++) /* nop */; |
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while(clock->status & 0x1) /* nop */; |
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clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F); |
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clock->cmden |= 1; |
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clock->cmd |= 1; |
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while(clock->status & 0x1) /* nop */; |
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clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F); |
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clock->cmden |= 1; |
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clock->cmd |= 1; |
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while(clock->status & 0x1) /* nop */; |
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clock->ctrl |= 1; |
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} |
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static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr) |
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{ |
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if (*bootcr & BOOT_PLL_ASYNC_MODE) { |
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// Async
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switch (clock_id) { |
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case TNETD7200_CLOCK_ID_DSP: |
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return ar7_ref_clock; |
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default: |
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return ar7_afe_clock; |
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} |
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} else { |
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// Sync
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if (*bootcr & BOOT_PLL_2TO1_MODE) { |
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// 2:1
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switch (clock_id) { |
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case TNETD7200_CLOCK_ID_DSP: |
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return ar7_ref_clock; |
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default: |
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return ar7_afe_clock; |
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} |
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} else { |
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// 1:1
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return ar7_ref_clock; |
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} |
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} |
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} |
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static void __init tnetd7200_init_clocks(void) |
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{ |
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u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); |
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struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
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int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv; |
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int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv; |
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int usb_base, usb_mul, usb_prediv, usb_postdiv; |
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ar7_cpu_clock = tnetd7200_get_clock(ar7_afe_clock, |
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&clocks->cpu, |
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bootcr, ar7_afe_clock); |
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/*
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Log from Fritz!Box 7170 Annex B: |
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CPU revision is: 00018448 |
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Clocks: Async mode |
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Clocks: Setting DSP clock |
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Clocks: prediv: 1, postdiv: 1, mul: 5 |
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Clocks: base = 25000000, frequency = 125000000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10 |
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Clocks: Setting CPU clock |
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Adjusted requested frequency 211000000 to 211968000 |
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Clocks: prediv: 1, postdiv: 1, mul: 6 |
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Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6 |
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Clocks: Setting USB clock |
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Adjusted requested frequency 48000000 to 48076920 |
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Clocks: prediv: 13, postdiv: 1, mul: 5 |
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Clocks: base = 125000000, frequency = 48000000, prediv = 13, postdiv = 1, postdiv2 = -1, mul = 5 |
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DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination, driver hung on startup. |
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Haven't tested this on a synchronous board, neither do i know what to do with ar7_dsp_clock |
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*/ |
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cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr); |
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dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr); |
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if (*bootcr & BOOT_PLL_ASYNC_MODE) { |
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ar7_bus_clock = 125000000; |
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printk("Clocks: Async mode\n"); |
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printk("Clocks: Setting DSP clock\n"); |
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calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul); |
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ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv; |
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
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ar7_bus_clock); |
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printk("Clocks: Setting CPU clock\n"); |
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calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul); |
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ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv; |
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tnetd7200_set_clock(cpu_base, &clocks->cpu,
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cpu_prediv, cpu_postdiv, -1, cpu_mul,
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ar7_cpu_clock); |
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} else { |
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if (*bootcr & BOOT_PLL_2TO1_MODE) { |
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printk("Clocks: Sync 2:1 mode\n"); |
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printk("Clocks: Setting CPU clock\n"); |
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calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul); |
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ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv; |
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tnetd7200_set_clock(cpu_base, &clocks->cpu,
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cpu_prediv, cpu_postdiv, -1, cpu_mul,
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ar7_cpu_clock); |
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printk("Clocks: Setting DSP clock\n"); |
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calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul); |
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ar7_bus_clock = ar7_cpu_clock / 2; |
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
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ar7_bus_clock); |
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} else { |
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ar7_bus_clock = ar7_cpu_clock; |
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printk("Clocks: Sync 1:1 mode\n"); |
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printk("Clocks: Setting DSP clock\n"); |
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calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul); |
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ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv; |
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
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ar7_bus_clock); |
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ar7_cpu_clock = ar7_bus_clock; |
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} |
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} |
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tnetd7200_set_clock(ar7_ref_clock * 5, &clocks->usb, |
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bootcr, 48000000); |
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printk("Clocks: Setting USB clock\n"); |
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usb_base = ar7_bus_clock; |
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calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, &usb_postdiv, &usb_mul); |
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tnetd7200_set_clock(usb_base, &clocks->usb,
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usb_prediv, usb_postdiv, -1, usb_mul,
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TNETD7200_DEF_USB_CLK); |
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if (ar7_dsp_clock == 250000000) |
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tnetd7200_set_clock(ar7_ref_clock, &clocks->dsp, |
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bootcr, ar7_dsp_clock); |
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#warning FIXME: ????! Hrmm |
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ar7_dsp_clock = ar7_cpu_clock; |
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iounmap(clocks); |
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iounmap(bootcr); |
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@ -347,11 +456,10 @@ void __init ar7_init_clocks(void) |
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{ |
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switch (ar7_chip_id()) { |
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case AR7_CHIP_7100: |
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#warning FIXME: Check if the new 7200 clock init works for 7100 |
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tnetd7200_init_clocks(); |
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break; |
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case AR7_CHIP_7200: |
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#warning FIXME: check revision |
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ar7_dsp_clock = 250000000; |
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tnetd7200_init_clocks(); |
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break; |
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case AR7_CHIP_7300: |
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