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@ -27,15 +27,13 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag) |
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return "?"; |
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return "?"; |
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} |
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} |
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#if 1 |
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#define AR71XX_PLL_VAL_1000 0x00110000 |
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#define PLL_VAL_1000 0x00110000 |
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#define AR71XX_PLL_VAL_100 0x00001099 |
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#define PLL_VAL_100 0x00001099 |
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#define AR71XX_PLL_VAL_10 0x00991099 |
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#define PLL_VAL_10 0x00991099 |
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#else |
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#define AR91XX_PLL_VAL_1000 0x1a000000 |
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#define PLL_VAL_1000 0x01111000 |
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#define AR91XX_PLL_VAL_100 0x13000a44 |
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#define PLL_VAL_100 0x09991000 |
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#define AR91XX_PLL_VAL_10 0x00441099 |
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#define PLL_VAL_10 0x09991999 |
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#endif |
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static void ag71xx_phy_link_update(struct ag71xx *ag) |
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static void ag71xx_phy_link_update(struct ag71xx *ag) |
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{ |
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{ |
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@ -67,26 +65,30 @@ static void ag71xx_phy_link_update(struct ag71xx *ag) |
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case SPEED_1000: |
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case SPEED_1000: |
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mii_speed = MII_CTRL_SPEED_1000; |
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mii_speed = MII_CTRL_SPEED_1000; |
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cfg2 |= MAC_CFG2_IF_1000; |
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cfg2 |= MAC_CFG2_IF_1000; |
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pll = PLL_VAL_1000; |
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pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000 |
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: AR71XX_PLL_VAL_1000; |
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fifo5 |= FIFO_CFG5_BM; |
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fifo5 |= FIFO_CFG5_BM; |
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break; |
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break; |
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case SPEED_100: |
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case SPEED_100: |
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mii_speed = MII_CTRL_SPEED_100; |
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mii_speed = MII_CTRL_SPEED_100; |
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cfg2 |= MAC_CFG2_IF_10_100; |
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cfg2 |= MAC_CFG2_IF_10_100; |
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ifctl |= MAC_IFCTL_SPEED; |
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ifctl |= MAC_IFCTL_SPEED; |
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pll = PLL_VAL_100; |
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pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100 |
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: AR71XX_PLL_VAL_100; |
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break; |
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break; |
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case SPEED_10: |
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case SPEED_10: |
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mii_speed = MII_CTRL_SPEED_10; |
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mii_speed = MII_CTRL_SPEED_10; |
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cfg2 |= MAC_CFG2_IF_10_100; |
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cfg2 |= MAC_CFG2_IF_10_100; |
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pll = PLL_VAL_10; |
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pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10 |
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: AR71XX_PLL_VAL_10; |
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break; |
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break; |
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default: |
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default: |
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BUG(); |
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BUG(); |
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return; |
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return; |
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} |
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} |
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); |
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, |
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pdata->is_ar91xx ? 0x780fff : 0x008001ff); |
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pdata->set_pll(pll); |
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pdata->set_pll(pll); |
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ag71xx_mii_ctrl_set_speed(ag, mii_speed); |
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ag71xx_mii_ctrl_set_speed(ag, mii_speed); |
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