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@ -36,6 +36,8 @@ |
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#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14) |
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#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14) |
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#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16) |
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#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16) |
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#define IFXMIPS_MEI_INT (INT_NUM_IM1_IRL0 + 23) |
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#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) |
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#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) |
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#define MIPS_CPU_TIMER_IRQ 7 |
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#define MIPS_CPU_TIMER_IRQ 7 |
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