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ar71xx: fix ethernet PLL setting on ar7242

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SVN-Revision: 28124
master
Felix Fietkau 13 years ago
parent eae76139f2
commit cd2c68501c
1 changed files with 5 additions and 3 deletions
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  1. 8
      target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

8
target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
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@ -265,9 +265,11 @@ static void ar724x_set_pll_ge1(int speed)
static void ar7242_set_pll_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
void __iomem *base;
ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK,
val, AR71XX_ETH0_PLL_SHIFT);
base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
__raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
iounmap(base);
}
static void ar91xx_set_pll_ge0(int speed)
@ -410,7 +412,7 @@ struct platform_device ar71xx_eth1_device = {
#define AR724X_PLL_VAL_100 0x00001099
#define AR724X_PLL_VAL_10 0x00991099
#define AR7242_PLL_VAL_1000 0x1c000000
#define AR7242_PLL_VAL_1000 0x16000000
#define AR7242_PLL_VAL_100 0x00000101
#define AR7242_PLL_VAL_10 0x00001616

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