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@ -1,10 +1,8 @@ |
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/*
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* $Id$ |
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* |
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* ADM5120 specific interrupt handlers |
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* |
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* Copyright (C) 2007 OpenWrt.org |
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org> |
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* Copyright (C) 2007-2008 OpenWrt.org |
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* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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@ -17,26 +15,34 @@ |
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#include <linux/version.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <linux/io.h> |
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#include <asm/irq.h> |
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#include <asm/irq_cpu.h> |
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#include <asm/mipsregs.h> |
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#include <asm/bitops.h> |
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#include <adm5120_defs.h> |
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#include <adm5120_irq.h> |
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#define INTC_WRITE(reg, val) __raw_writel((val), \ |
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(void __iomem *)(KSEG1ADDR(ADM5120_INTC_BASE) + reg)) |
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#define INTC_READ(reg) __raw_readl(\ |
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(void __iomem *)(KSEG1ADDR(ADM5120_INTC_BASE) + reg)) |
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#include <asm/mach-adm5120/adm5120_defs.h> |
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#include <asm/mach-adm5120/adm5120_irq.h> |
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static void adm5120_intc_irq_unmask(unsigned int irq); |
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static void adm5120_intc_irq_mask(unsigned int irq); |
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type); |
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static inline void intc_write_reg(unsigned int reg, u32 val) |
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{ |
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void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE); |
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__raw_writel(val, base + reg); |
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} |
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static inline u32 intc_read_reg(unsigned int reg) |
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{ |
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void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE); |
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return __raw_readl(base + reg); |
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} |
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static struct irq_chip adm5120_intc_irq_chip = { |
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.name = "INTC", |
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.unmask = adm5120_intc_irq_unmask, |
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@ -53,13 +59,13 @@ static struct irqaction adm5120_intc_irq_action = { |
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static void adm5120_intc_irq_unmask(unsigned int irq) |
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{ |
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irq -= ADM5120_INTC_IRQ_BASE; |
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INTC_WRITE(INTC_REG_IRQ_ENABLE, 1 << irq); |
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intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq); |
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} |
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static void adm5120_intc_irq_mask(unsigned int irq) |
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{ |
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irq -= ADM5120_INTC_IRQ_BASE; |
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INTC_WRITE(INTC_REG_IRQ_DISABLE, 1 << irq); |
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intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq); |
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} |
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type) |
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@ -94,13 +100,13 @@ static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type) |
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switch (irq) { |
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case ADM5120_IRQ_GPIO2: |
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case ADM5120_IRQ_GPIO4: |
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mode = INTC_READ(INTC_REG_INT_MODE); |
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mode = intc_read_reg(INTC_REG_INT_MODE); |
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if (sense == IRQ_TYPE_LEVEL_LOW) |
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mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE)); |
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else |
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mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE)); |
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INTC_WRITE(INTC_REG_INT_MODE, mode); |
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intc_write_reg(INTC_REG_INT_MODE, mode); |
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/* fallthrough */ |
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default: |
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irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; |
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@ -117,7 +123,7 @@ static void adm5120_intc_irq_dispatch(void) |
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int irq; |
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/* dispatch only one IRQ at a time */ |
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status = INTC_READ(INTC_REG_IRQ_STATUS) & INTC_INT_ALL; |
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status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL; |
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if (status) { |
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irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1; |
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@ -142,21 +148,21 @@ asmlinkage void plat_irq_dispatch(void) |
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#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) |
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static void __init adm5120_intc_irq_init(int base) |
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static void __init adm5120_intc_irq_init(void) |
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{ |
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int i; |
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/* disable all interrupts */ |
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INTC_WRITE(INTC_REG_IRQ_DISABLE, INTC_INT_ALL); |
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intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL); |
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/* setup all interrupts to generate IRQ instead of FIQ */ |
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INTC_WRITE(INTC_REG_INT_MODE, 0); |
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intc_write_reg(INTC_REG_INT_MODE, 0); |
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/* set active level for all external interrupts to HIGH */ |
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INTC_WRITE(INTC_REG_INT_LEVEL, 0); |
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intc_write_reg(INTC_REG_INT_LEVEL, 0); |
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/* disable usage of the TEST_SOURCE register */ |
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INTC_WRITE(INTC_REG_IRQ_SOURCE_SELECT, 0); |
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intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0); |
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for (i = ADM5120_INTC_IRQ_BASE; |
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i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST; |
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@ -171,5 +177,5 @@ static void __init adm5120_intc_irq_init(int base) |
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void __init arch_init_irq(void) { |
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mips_cpu_irq_init(); |
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adm5120_intc_irq_init(ADM5120_INTC_IRQ_BASE); |
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adm5120_intc_irq_init(); |
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} |
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