The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X register file") introduced definitions for some bits in the RDV/RXD part of the ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit only specified the lower bits. The upper bits also have to be unset when the lower bits should only be set. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 45522master
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