John Crispin
7 years ago
committed by
Mathias Kresin
parent
20d63ebc94
commit
b7f115f22a
@ -1,110 +0,0 @@ |
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# The U-Boot loader of the OpenMesh devices requires image sizes and |
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# checksums to be provided in the U-Boot environment. |
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# The OpenMesh devices come with 2 main partitions - while one is active |
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# sysupgrade will flash the other. The boot order is changed to boot the |
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# newly flashed partition. If the new partition can't be booted due to |
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# upgrade failures the previously used partition is loaded. |
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|
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platform_do_upgrade_openmesh() { |
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local tar_file="$1" |
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local restore_backup |
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local primary_kernel_mtd |
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|
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local setenv_script="/tmp/fw_env_upgrade" |
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|
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local kernel_mtd="$(find_mtd_index $PART_NAME)" |
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local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)" |
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local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)" |
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|
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# detect to which flash region the new image is written to. |
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# |
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# 1. check what is the mtd index for the first flash region on this |
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# device |
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# 2. check if the target partition ("inactive") has the mtd index of |
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# the first flash region |
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# |
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# - when it is: the new bootseq will be 1,2 and the first region is |
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# modified |
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# - when it isnt: bootseq will be 2,1 and the second region is |
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# modified |
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# |
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# The detection has to be done via the hardcoded mtd partition because |
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# the current boot might be done with the fallback region. Let us |
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# assume that the current bootseq is 1,2. The bootloader detected that |
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# the image in flash region 1 is corrupt and thus switches to flash |
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# region 2. The bootseq in the u-boot-env is now still the same and |
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# the sysupgrade code can now only rely on the actual mtd indexes and |
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# not the bootseq variable to detect the currently booted flash |
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# region/image. |
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# |
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# In the above example, an implementation which uses bootseq ("1,2") to |
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# detect the currently booted image would assume that region 1 is booted |
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# and then overwrite the variables for the wrong flash region (aka the |
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# one which isn't modified). This could result in a device which doesn't |
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# boot anymore to Linux until it was reflashed with ap51-flash. |
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local next_boot_part="1" |
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case "$(board_name)" in |
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openmesh,a42) |
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primary_kernel_mtd=8 |
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;; |
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*) |
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echo "failed to detect primary kernel mtd partition for board" |
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return 1 |
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;; |
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esac |
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[ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2" |
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|
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local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$') |
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board_dir=${board_dir%/} |
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|
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local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c) |
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local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c) |
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# rootfs without EOF marker |
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rootfs_length=$((rootfs_length-4)) |
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|
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local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}" |
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# md5 checksum of rootfs with EOF marker |
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local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}" |
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|
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# |
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# add tar support to get_image() to use default_do_upgrade() instead? |
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# |
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|
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# take care of restoring a saved config |
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[ "$SAVE_CONFIG" -eq 1 ] && restore_backup="${MTD_CONFIG_ARGS} -j ${CONF_TAR}" |
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|
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# write concatinated kernel + rootfs to flash |
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tar xf $tar_file ${board_dir}/kernel ${board_dir}/root -O | \ |
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mtd $restore_backup write - $PART_NAME |
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|
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# prepare new u-boot env |
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if [ "$next_boot_part" = "1" ]; then |
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echo "bootseq 1,2" > $setenv_script |
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else |
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echo "bootseq 2,1" > $setenv_script |
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fi |
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|
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printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script |
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printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script |
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printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script |
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printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script |
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|
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printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script |
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printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script |
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printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script |
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printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script |
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|
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# store u-boot env changes |
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fw_setenv -s $setenv_script || { |
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echo "failed to update U-Boot environment" |
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return 1 |
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} |
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} |
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|
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# create /var/lock for the lock "fw_setenv.lock" of fw_setenv |
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# the rest is copied using ipq806x's RAMFS_COPY_BIN and RAMFS_COPY_DATA |
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platform_add_ramfs_ubootenv() |
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{ |
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mkdir -p $RAM_ROOT/var/lock |
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} |
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append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv |
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@ -1,244 +0,0 @@ |
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
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* Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com> |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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* |
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*/ |
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|
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#include "qcom-ipq4019.dtsi" |
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#include "qcom-ipq4019-bus.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/soc/qcom,tcsr.h> |
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|
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/ { |
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model = "OpenMesh A42"; |
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compatible = "openmesh,a42", "qcom,ipq4019"; |
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|
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reserved-memory { |
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#address-cells = <0x1>; |
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#size-cells = <0x1>; |
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ranges; |
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|
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rsvd1@87000000 { |
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reg = <0x87000000 0x500000>; |
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no-map; |
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}; |
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|
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wifi_dump@87500000 { |
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reg = <0x87500000 0x600000>; |
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no-map; |
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}; |
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|
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rsvd2@87B00000 { |
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reg = <0x87b00000 0x500000>; |
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no-map; |
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}; |
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}; |
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|
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soc { |
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tcsr@194b000 { |
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/* select hostmode */ |
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compatible = "qcom,tcsr"; |
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reg = <0x194b000 0x100>; |
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qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>; |
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status = "ok"; |
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}; |
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|
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ess_tcsr@1953000 { |
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compatible = "qcom,tcsr"; |
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reg = <0x1953000 0x1000>; |
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qcom,ess-interface-select = <TCSR_ESS_PSGMII>; |
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}; |
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|
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tcsr@1949000 { |
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compatible = "qcom,tcsr"; |
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reg = <0x1949000 0x100>; |
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qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>; |
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}; |
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|
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tcsr@1957000 { |
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compatible = "qcom,tcsr"; |
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reg = <0x1957000 0x100>; |
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qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>; |
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}; |
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|
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pinctrl@1000000 { |
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serial_pins: serial_pinmux { |
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mux { |
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pins = "gpio60", "gpio61"; |
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function = "blsp_uart0"; |
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bias-disable; |
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}; |
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}; |
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|
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spi_0_pins: spi_0_pinmux { |
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pinmux { |
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function = "blsp_spi0"; |
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pins = "gpio55", "gpio56", "gpio57"; |
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}; |
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pinmux_cs { |
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function = "gpio"; |
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pins = "gpio54"; |
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}; |
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pinconf { |
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pins = "gpio55", "gpio56", "gpio57"; |
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drive-strength = <12>; |
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bias-disable; |
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}; |
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pinconf_cs { |
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pins = "gpio54"; |
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drive-strength = <2>; |
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bias-disable; |
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output-high; |
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}; |
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}; |
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}; |
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|
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blsp_dma: dma@7884000 { |
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status = "ok"; |
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}; |
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|
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spi_0: spi@78b5000 { |
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pinctrl-0 = <&spi_0_pins>; |
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pinctrl-names = "default"; |
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status = "ok"; |
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cs-gpios = <&tlmm 54 0>; |
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|
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m25p80@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <24000000>; |
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|
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/* partitions are passed via bootloader */ |
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}; |
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}; |
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|
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serial@78af000 { |
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pinctrl-0 = <&serial_pins>; |
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pinctrl-names = "default"; |
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status = "ok"; |
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}; |
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|
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cryptobam: dma@8e04000 { |
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status = "ok"; |
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}; |
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|
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crypto@8e3a000 { |
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status = "ok"; |
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}; |
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|
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watchdog@b017000 { |
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status = "ok"; |
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}; |
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|
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usb2_hs_phy: hsphy@a8000 { |
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status = "ok"; |
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}; |
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|
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usb2: usb2@60f8800 { |
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status = "ok"; |
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}; |
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|
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mdio@90000 { |
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status = "okay"; |
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}; |
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|
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ess-switch@c000000 { |
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status = "okay"; |
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}; |
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|
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ess-psgmii@98000 { |
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status = "okay"; |
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}; |
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|
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edma@c080000 { |
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status = "okay"; |
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}; |
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|
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wifi@a000000 { |
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status = "okay"; |
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qcom,ath10k-calibration-variant = "OM-A42"; |
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}; |
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|
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wifi@a800000 { |
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status = "okay"; |
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qcom,ath10k-calibration-variant = "OM-A42"; |
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}; |
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}; |
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|
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gpio-keys { |
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compatible = "gpio-keys"; |
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|
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reset { |
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label = "reset"; |
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gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; |
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linux,code = <KEY_RESTART>; |
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}; |
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}; |
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|
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aliases { |
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led-boot = &power; |
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led-failsafe = &power; |
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led-running = &power; |
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led-upgrade = &power; |
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}; |
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|
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gpio-leds { |
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compatible = "gpio-leds"; |
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|
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red { |
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label = "a42:red:status"; |
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gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; |
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linux,default-trigger = "default-off"; |
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}; |
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|
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power: green { |
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label = "a42:green:status"; |
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gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>; |
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}; |
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|
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blue { |
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label = "a42:blue:status"; |
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gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; |
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linux,default-trigger = "default-off"; |
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}; |
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}; |
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|
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watchdog { |
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compatible = "linux,wdt-gpio"; |
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gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; |
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hw_algo = "toggle"; |
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/* hw_margin_ms is actually 300s but driver limits it to 60s */ |
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hw_margin_ms = <60000>; |
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always-running; |
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}; |
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}; |
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|
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&gmac0 { |
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qcom,phy_mdio_addr = <4>; |
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qcom,poll_required = <1>; |
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qcom,forced_speed = <1000>; |
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qcom,forced_duplex = <1>; |
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vlan_tag = <2 0x20>; |
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}; |
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|
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&gmac1 { |
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qcom,phy_mdio_addr = <3>; |
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qcom,poll_required = <1>; |
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qcom,forced_speed = <1000>; |
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qcom,forced_duplex = <1>; |
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vlan_tag = <1 0x10>; |
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}; |
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File diff suppressed because it is too large
Load Diff
@ -1,322 +0,0 @@ |
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
||||
* copyright notice and this permission notice appear in all copies. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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* |
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*/ |
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|
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#include "qcom-ipq4019.dtsi" |
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#include "qcom-ipq4019-bus.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/soc/qcom,tcsr.h> |
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|
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/ { |
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model = "AVM FRITZ!Box 4040"; |
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compatible = "avm,fritzbox-4040", "qcom,ipq4019"; |
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|
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aliases { |
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led-boot = &power; |
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led-failsafe = &flash; |
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led-running = &power; |
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led-upgrade = &flash; |
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}; |
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|
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reserved-memory { |
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#address-cells = <0x1>; |
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#size-cells = <0x1>; |
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ranges; |
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|
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tz_apps@87b80000 { |
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reg = <0x87b80000 0x280000>; |
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reusable; |
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}; |
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|
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smem@87e00000 { |
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reg = <0x87e00000 0x080000>; |
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no-map; |
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}; |
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|
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tz@87e80000 { |
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reg = <0x87e80000 0x180000>; |
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no-map; |
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}; |
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}; |
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|
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soc { |
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mdio@90000 { |
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status = "okay"; |
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}; |
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|
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ess-psgmii@98000 { |
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status = "okay"; |
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}; |
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|
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tcsr@1949000 { |
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compatible = "qcom,tcsr"; |
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reg = <0x1949000 0x100>; |
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qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>; |
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}; |
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|
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tcsr@194b000 { |
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compatible = "qcom,tcsr"; |
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reg = <0x194b000 0x100>; |
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qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>; |
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}; |
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|
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ess_tcsr@1953000 { |
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compatible = "qcom,tcsr"; |
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reg = <0x1953000 0x1000>; |
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qcom,ess-interface-select = <TCSR_ESS_PSGMII>; |
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}; |
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|
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tcsr@1957000 { |
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compatible = "qcom,tcsr"; |
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reg = <0x1957000 0x100>; |
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qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>; |
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}; |
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|
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usb2@60f8800 { |
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status = "ok"; |
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}; |
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|
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serial@78af000 { |
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pinctrl-0 = <&serial_pins>; |
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pinctrl-names = "default"; |
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status = "ok"; |
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}; |
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|
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usb3@8af8800 { |
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status = "ok"; |
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}; |
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|
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crypto@8e3a000 { |
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status = "ok"; |
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}; |
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|
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wifi@a000000 { |
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status = "okay"; |
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}; |
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|
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wifi@a800000 { |
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status = "okay"; |
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}; |
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|
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watchdog@b017000 { |
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status = "ok"; |
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}; |
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|
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qca8075: ess-switch@c000000 { |
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status = "okay"; |
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|
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#gpio-cells = <2>; |
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gpio-controller; |
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|
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enable-usb-power { |
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gpio-hog; |
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line-name = "enable USB3 power"; |
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gpios = <7 GPIO_ACTIVE_HIGH>; |
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output-high; |
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}; |
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}; |
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|
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edma@c080000 { |
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status = "okay"; |
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}; |
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}; |
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|
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gpio-keys { |
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compatible = "gpio-keys"; |
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|
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wlan { |
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label = "wlan"; |
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gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; |
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linux,code = <KEY_RFKILL>; |
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}; |
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|
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wps { |
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label = "wps"; |
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gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; |
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linux,code = <KEY_WPS_BUTTON>; |
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}; |
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}; |
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|
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gpio-leds { |
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compatible = "gpio-leds"; |
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|
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wlan { |
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label = "fritz4040:green:wlan"; |
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gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>; |
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}; |
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|
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panic: info_red { |
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label = "fritz4040:red:info"; |
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gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>; |
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panic-indicator; |
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}; |
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|
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wan { |
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label = "fritz4040:green:wan"; |
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gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>; |
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}; |
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|
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power: power { |
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label = "fritz4040:green:power"; |
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gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>; |
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}; |
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|
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lan { |
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label = "fritz4040:green:lan"; |
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gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>; |
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}; |
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|
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flash: info_amber { |
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label = "fritz4040:amber:info"; |
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gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>; |
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}; |
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}; |
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}; |
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|
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&tlmm { |
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serial_pins: serial_pinmux { |
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mux { |
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pins = "gpio60", "gpio61"; |
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function = "blsp_uart0"; |
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bias-disable; |
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}; |
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}; |
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|
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spi_0_pins: spi_0_pinmux { |
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mux { |
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function = "blsp_spi0"; |
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pins = "gpio55", "gpio56", "gpio57"; |
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drive-strength = <12>; |
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bias-disable; |
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}; |
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|
||||
mux_cs { |
||||
function = "gpio"; |
||||
pins = "gpio54"; |
||||
drive-strength = <2>; |
||||
bias-disable; |
||||
output-high; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&cryptobam { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
&blsp_dma { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
&spi_0 { /* BLSP1 QUP1 */ |
||||
pinctrl-0 = <&spi_0_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "ok"; |
||||
cs-gpios = <&tlmm 54 0>; |
||||
|
||||
mx25l25635f@0 { |
||||
compatible = "jedec,spi-nor"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0>; |
||||
spi-max-frequency = <24000000>; |
||||
status = "ok"; |
||||
m25p,fast-read; |
||||
|
||||
partitions { |
||||
compatible = "fixed-partitions"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
partition0@0 { |
||||
label = "SBL1"; |
||||
reg = <0x00000000 0x00040000>; |
||||
read-only; |
||||
}; |
||||
partition1@40000 { |
||||
label = "MIBIB"; |
||||
reg = <0x00040000 0x00020000>; |
||||
read-only; |
||||
}; |
||||
partition2@60000 { |
||||
label = "QSEE"; |
||||
reg = <0x00060000 0x00060000>; |
||||
read-only; |
||||
}; |
||||
partition3@c0000 { |
||||
label = "CDT"; |
||||
reg = <0x000c0000 0x00010000>; |
||||
read-only; |
||||
}; |
||||
partition4@d0000 { |
||||
label = "DDRPARAMS"; |
||||
reg = <0x000d0000 0x00010000>; |
||||
read-only; |
||||
}; |
||||
partition5@e0000 { |
||||
label = "APPSBLENV"; /* uboot env - empty */ |
||||
reg = <0x000e0000 0x00010000>; |
||||
read-only; |
||||
}; |
||||
partition6@f0000 { |
||||
label = "urlader"; /* APPSBL */ |
||||
reg = <0x000f0000 0x0002dc000>; |
||||
read-only; |
||||
}; |
||||
partition7@11dc00 { |
||||
/* make a backup of this partition! */ |
||||
label = "urlader_config"; |
||||
reg = <0x0011dc00 0x00002400>; |
||||
read-only; |
||||
}; |
||||
partition8@120000 { |
||||
label = "tffs1"; |
||||
reg = <0x00120000 0x00080000>; |
||||
read-only; |
||||
}; |
||||
partition9@1a0000 { |
||||
label = "tffs2"; |
||||
reg = <0x001a0000 0x00080000>; |
||||
read-only; |
||||
}; |
||||
partition10@220000 { |
||||
label = "uboot"; |
||||
reg = <0x00220000 0x00080000>; |
||||
read-only; |
||||
}; |
||||
partition11@2A0000 { |
||||
label = "firmware"; |
||||
reg = <0x002a0000 0x01c60000>; |
||||
}; |
||||
partition12@1f00000 { |
||||
label = "jffs2"; |
||||
reg = <0x01f00000 0x00100000>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&usb3_ss_phy { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
&usb3_hs_phy { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
&usb2_hs_phy { |
||||
status = "ok"; |
||||
}; |
||||
@ -1,316 +0,0 @@ |
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
||||
* |
||||
* Permission to use, copy, modify, and/or distribute this software for any |
||||
* purpose with or without fee is hereby granted, provided that the above |
||||
* copyright notice and this permission notice appear in all copies. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
||||
* |
||||
*/ |
||||
|
||||
#include "qcom-ipq4019.dtsi" |
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/input/input.h> |
||||
#include <dt-bindings/soc/qcom,tcsr.h> |
||||
|
||||
/ { |
||||
model = "GL.iNet GL-B1300"; |
||||
compatible = "glinet,gl-b1300", "qcom,ipq4019"; |
||||
|
||||
memory { |
||||
device_type = "memory"; |
||||
reg = <0x80000000 0x10000000>; |
||||
}; |
||||
|
||||
reserved-memory { |
||||
#address-cells = <0x1>; |
||||
#size-cells = <0x1>; |
||||
ranges; |
||||
|
||||
apps_bl@87000000 { |
||||
reg = <0x87000000 0x400000>; |
||||
no-map; |
||||
}; |
||||
|
||||
sbl@87400000 { |
||||
reg = <0x87400000 0x100000>; |
||||
no-map; |
||||
}; |
||||
|
||||
cnss_debug@87500000 { |
||||
reg = <0x87500000 0x600000>; |
||||
no-map; |
||||
}; |
||||
|
||||
cpu_context_dump@87b00000 { |
||||
reg = <0x87b00000 0x080000>; |
||||
no-map; |
||||
}; |
||||
|
||||
tz_apps@87b80000 { |
||||
reg = <0x87b80000 0x280000>; |
||||
no-map; |
||||
}; |
||||
|
||||
smem@87e00000 { |
||||
reg = <0x87e00000 0x080000>; |
||||
no-map; |
||||
}; |
||||
|
||||
tz@87e80000 { |
||||
reg = <0x87e80000 0x180000>; |
||||
no-map; |
||||
}; |
||||
}; |
||||
|
||||
soc { |
||||
tcsr@194b000 { |
||||
/* select hostmode */ |
||||
compatible = "qcom,tcsr"; |
||||
reg = <0x194b000 0x100>; |
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>; |
||||
status = "ok"; |
||||
}; |
||||
|
||||
ess_tcsr@1953000 { |
||||
compatible = "qcom,tcsr"; |
||||
reg = <0x1953000 0x1000>; |
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>; |
||||
}; |
||||
|
||||
tcsr@1949000 { |
||||
compatible = "qcom,tcsr"; |
||||
reg = <0x1949000 0x100>; |
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>; |
||||
}; |
||||
|
||||
tcsr@1957000 { |
||||
compatible = "qcom,tcsr"; |
||||
reg = <0x1957000 0x100>; |
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>; |
||||
}; |
||||
|
||||
pinctrl@1000000 { |
||||
serial_pins: serial_pinmux { |
||||
mux { |
||||
pins = "gpio60", "gpio61"; |
||||
function = "blsp_uart0"; |
||||
bias-disable; |
||||
}; |
||||
}; |
||||
|
||||
spi_0_pins: spi_0_pinmux { |
||||
pinmux { |
||||
function = "blsp_spi0"; |
||||
pins = "gpio55", "gpio56", "gpio57"; |
||||
}; |
||||
pinmux_cs { |
||||
function = "gpio"; |
||||
pins = "gpio54"; |
||||
}; |
||||
pinconf { |
||||
pins = "gpio55", "gpio56", "gpio57"; |
||||
drive-strength = <12>; |
||||
bias-disable; |
||||
}; |
||||
pinconf_cs { |
||||
pins = "gpio54"; |
||||
drive-strength = <2>; |
||||
bias-disable; |
||||
output-high; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
blsp_dma: dma@7884000 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
spi_0: spi@78b5000 { |
||||
pinctrl-0 = <&spi_0_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "ok"; |
||||
cs-gpios = <&tlmm 54 0>; |
||||
}; |
||||
|
||||
serial@78af000 { |
||||
pinctrl-0 = <&serial_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "ok"; |
||||
}; |
||||
|
||||
cryptobam: dma@8e04000 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
crypto@8e3a000 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
watchdog@b017000 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
usb3_ss_phy: ssphy@9a000 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
usb3_hs_phy: hsphy@a6000 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
usb3: usb3@8af8800 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
usb2_hs_phy: hsphy@a8000 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
usb2: usb2@60f8800 { |
||||
status = "ok"; |
||||
}; |
||||
|
||||
mdio@90000 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
ess-switch@c000000 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
ess-psgmii@98000 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
edma@c080000 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
wifi@a000000 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
wifi@a800000 { |
||||
status = "okay"; |
||||
}; |
||||
}; |
||||
|
||||
gpio-keys { |
||||
compatible = "gpio-keys"; |
||||
|
||||
wps { |
||||
label = "wps"; |
||||
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; |
||||
linux,code = <KEY_WPS_BUTTON>; |
||||
}; |
||||
reset { |
||||
label = "reset"; |
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; |
||||
linux,code = <KEY_RESTART>; |
||||
}; |
||||
}; |
||||
|
||||
gpio-leds { |
||||
compatible = "gpio-leds"; |
||||
|
||||
power { |
||||
label = "gl-b1300:green:power"; |
||||
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>; |
||||
default-state = "on"; |
||||
}; |
||||
mesh { |
||||
label = "gl-b1300:green:mesh"; |
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
wlan { |
||||
label = "gl-b1300:green:wlan"; |
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&spi_0 { |
||||
mx25l25635f@0 { |
||||
compatible = "mx25l25635f", "jedec,spi-nor"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0>; |
||||
spi-max-frequency = <24000000>; |
||||
|
||||
SBL1@0 { |
||||
label = "SBL1"; |
||||
reg = <0x0 0x40000>; |
||||
read-only; |
||||
}; |
||||
MIBIB@40000 { |
||||
label = "MIBIB"; |
||||
reg = <0x40000 0x20000>; |
||||
read-only; |
||||
}; |
||||
QSEE@60000 { |
||||
label = "QSEE"; |
||||
reg = <0x60000 0x60000>; |
||||
read-only; |
||||
}; |
||||
CDT@c0000 { |
||||
label = "CDT"; |
||||
reg = <0xc0000 0x10000>; |
||||
read-only; |
||||
}; |
||||
DDRPARAMS@d0000 { |
||||
label = "DDRPARAMS"; |
||||
reg = <0xd0000 0x10000>; |
||||
read-only; |
||||
}; |
||||
APPSBLENV@e0000 { |
||||
label = "APPSBLENV"; |
||||
reg = <0xe0000 0x10000>; |
||||
read-only; |
||||
}; |
||||
APPSBL@f0000 { |
||||
label = "APPSBL"; |
||||
reg = <0xf0000 0x80000>; |
||||
read-only; |
||||
}; |
||||
ART@170000 { |
||||
label = "ART"; |
||||
reg = <0x170000 0x10000>; |
||||
read-only; |
||||
}; |
||||
kernel@180000 { |
||||
label = "kernel"; |
||||
reg = <0x180000 0x400000>; |
||||
}; |
||||
rootfs@580000 { |
||||
label = "rootfs"; |
||||
reg = <0x580000 0x1a80000>; |
||||
}; |
||||
firmware@180000 { |
||||
label = "firmware"; |
||||
reg = <0x180000 0x1e80000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&gmac0 { |
||||
qcom,phy_mdio_addr = <4>; |
||||
qcom,poll_required = <1>; |
||||
qcom,forced_speed = <1000>; |
||||
qcom,forced_duplex = <1>; |
||||
vlan_tag = <2 0x20>; |
||||
}; |
||||
|
||||
&gmac1 { |
||||
qcom,phy_mdio_addr = <3>; |
||||
qcom,poll_required = <1>; |
||||
qcom,forced_speed = <1000>; |
||||
qcom,forced_duplex = <1>; |
||||
vlan_tag = <1 0x10>; |
||||
}; |
||||
@ -1,27 +0,0 @@ |
||||
From 5543e93f51d5e23f9b3a7fe11a722c91fc410485 Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Wed, 13 Apr 2016 14:03:14 -0500
|
||||
Subject: [PATCH 15/69] cpufreq: dt: qcom: ipq4019: Add compat for qcom ipq4019
|
||||
|
||||
Instantiate cpufreq-dt-platdev driver for ipq4019 to support changing
|
||||
CPU frequencies.
|
||||
|
||||
This depends on Viresh Kumar's patches in this series:
|
||||
http://comments.gmane.org/gmane.linux.power-management.general/73887
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
---
|
||||
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
|
||||
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
|
||||
@@ -35,6 +35,8 @@ static const struct of_device_id machine
|
||||
|
||||
{ .compatible = "marvell,berlin", },
|
||||
|
||||
+ { .compatible = "qcom,ipq4019", },
|
||||
+
|
||||
{ .compatible = "samsung,exynos3250", },
|
||||
{ .compatible = "samsung,exynos4210", },
|
||||
{ .compatible = "samsung,exynos4212", },
|
||||
@ -1,33 +0,0 @@ |
||||
From 5e2df5f44e35d79fff2ab8bbb8a726ad5de78a3e Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
||||
Date: Thu, 28 Apr 2016 12:55:08 -0500
|
||||
Subject: [PATCH 16/69] clk: ipq4019: report accurate fixed clock rates
|
||||
|
||||
This looks like a copy-and-paste gone wrong, but update all
|
||||
the fixed clock rates to report the correct values.
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq4019.c | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq4019.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq4019.c
|
||||
@@ -1327,12 +1327,12 @@ static int gcc_ipq4019_probe(struct plat
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
- clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
|
||||
- clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
|
||||
- clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
|
||||
- clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
|
||||
+ clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000);
|
||||
+ clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000);
|
||||
+ clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 250000000);
|
||||
+ clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 250000000);
|
||||
clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
|
||||
- clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
|
||||
+ clk_register_fixed_rate(dev, "fepll500", "xo", 0, 500000000);
|
||||
clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
|
||||
|
||||
return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
|
||||
@ -1,77 +0,0 @@ |
||||
From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Thu, 17 Mar 2016 15:01:09 -0500
|
||||
Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
|
||||
support
|
||||
|
||||
This adds some operating points for cpu frequeny scaling
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
|
||||
1 file changed, 26 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -40,14 +40,7 @@
|
||||
reg = <0x0>;
|
||||
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
||||
clock-frequency = <0>;
|
||||
- operating-points = <
|
||||
- /* kHz uV (fixed) */
|
||||
- 48000 1100000
|
||||
- 200000 1100000
|
||||
- 500000 1100000
|
||||
- 666000 1100000
|
||||
- >;
|
||||
- clock-latency = <256000>;
|
||||
+ operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
@@ -59,6 +52,7 @@
|
||||
reg = <0x1>;
|
||||
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
||||
clock-frequency = <0>;
|
||||
+ operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
@@ -70,6 +64,7 @@
|
||||
reg = <0x2>;
|
||||
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
||||
clock-frequency = <0>;
|
||||
+ operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
@@ -81,6 +76,29 @@
|
||||
reg = <0x3>;
|
||||
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
||||
clock-frequency = <0>;
|
||||
+ operating-points-v2 = <&cpu0_opp_table>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpu0_opp_table: opp_table0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp@48000000 {
|
||||
+ opp-hz = /bits/ 64 <48000000>;
|
||||
+ clock-latency-ns = <256000>;
|
||||
+ };
|
||||
+ opp@200000000 {
|
||||
+ opp-hz = /bits/ 64 <200000000>;
|
||||
+ clock-latency-ns = <256000>;
|
||||
+ };
|
||||
+ opp@500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ clock-latency-ns = <256000>;
|
||||
+ };
|
||||
+ opp@666000000 {
|
||||
+ opp-hz = /bits/ 64 <666000000>;
|
||||
+ clock-latency-ns = <256000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,23 +0,0 @@ |
||||
From 71f82049dca86bc89b9da07e051e4ed492820233 Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Mon, 28 Mar 2016 11:16:51 -0500
|
||||
Subject: [PATCH 18/69] qcom: ipq4019: turn on DMA for i2c
|
||||
|
||||
These are the required nodes for i2c-qup to use DMA
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -179,6 +179,8 @@
|
||||
clock-names = "iface", "core";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
|
||||
+ dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1,28 +0,0 @@ |
||||
From 7292bf171cdf2fb48607058f12ddd0d812a87428 Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
||||
Date: Fri, 29 Apr 2016 12:48:02 -0500
|
||||
Subject: [PATCH 19/69] qcom: ipq4019: use correct clock for i2c bus 0
|
||||
|
||||
For the record the mapping is as follows:
|
||||
|
||||
QUP0 = SPI QUP1
|
||||
QUP1 = SPI QUP2
|
||||
QUP2 = I2C QUP1
|
||||
QUP3 = I2C QUP2
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -175,7 +175,7 @@
|
||||
reg = <0x78b7000 0x6000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||
+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -1,23 +0,0 @@ |
||||
From 4593e768393b9589f0a8987eaf57316c214865fe Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Mon, 11 Apr 2016 14:49:12 -0500
|
||||
Subject: [PATCH 20/69] qcom: ipq4019: enable DMA for spi
|
||||
|
||||
These are the required nodes for spi-qup to use DMA
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -167,6 +167,8 @@
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
|
||||
+ dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1,225 +0,0 @@ |
||||
From ec3e465ecf3f7dd26f2e22170e4c5f4b9979df5d Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Mon, 21 Mar 2016 15:55:21 -0500
|
||||
Subject: [PATCH 26/69] dts: ipq4019: Add support for IPQ4019 DK04 board
|
||||
|
||||
This is pretty similiar to a DK01 but has a bit more IO. Some notable
|
||||
differences are listed below however they are not in the device tree yet
|
||||
as we continue adding more support
|
||||
|
||||
- second serial port
|
||||
- PCIe
|
||||
- NAND
|
||||
- SD/EMMC
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/Makefile | 1 +
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 12 +-
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 21 +++
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 163 ++++++++++++++++++++++++
|
||||
4 files changed, 189 insertions(+), 8 deletions(-)
|
||||
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
|
||||
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -617,6 +617,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-apq8084-ifc6540.dtb \
|
||||
qcom-apq8084-mtp.dtb \
|
||||
qcom-ipq4019-ap.dk01.1-c1.dtb \
|
||||
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
|
||||
qcom-ipq8064-ap148.dtb \
|
||||
qcom-msm8660-surf.dtb \
|
||||
qcom-msm8960-cdp.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
|
||||
@@ -0,0 +1,22 @@
|
||||
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * Permission to use, copy, modify, and/or distribute this software for any
|
||||
+ * purpose with or without fee is hereby granted, provided that the above
|
||||
+ * copyright notice and this permission notice appear in all copies.
|
||||
+ *
|
||||
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
|
||||
+ compatible = "qcom,ap-dk04.1-c1", "qcom,ipq4019";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
@@ -0,0 +1,163 @@
|
||||
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * Permission to use, copy, modify, and/or distribute this software for any
|
||||
+ * purpose with or without fee is hereby granted, provided that the above
|
||||
+ * copyright notice and this permission notice appear in all copies.
|
||||
+ *
|
||||
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#include "qcom-ipq4019.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
|
||||
+ compatible = "qcom,ipq4019";
|
||||
+
|
||||
+ clocks {
|
||||
+ xo: xo {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <48000000>;
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ soc {
|
||||
+ timer {
|
||||
+ compatible = "arm,armv7-timer";
|
||||
+ interrupts = <1 2 0xf08>,
|
||||
+ <1 3 0xf08>,
|
||||
+ <1 4 0xf08>,
|
||||
+ <1 1 0xf08>;
|
||||
+ clock-frequency = <48000000>;
|
||||
+ };
|
||||
+
|
||||
+ pinctrl@0x01000000 {
|
||||
+ serial_0_pins: serial_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio16", "gpio17";
|
||||
+ function = "blsp_uart0";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ serial_1_pins: serial1_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio8", "gpio9";
|
||||
+ function = "blsp_uart1";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ spi_0_pins: spi_0_pinmux {
|
||||
+ pinmux {
|
||||
+ function = "blsp_spi0";
|
||||
+ pins = "gpio13", "gpio14", "gpio15";
|
||||
+ };
|
||||
+ pinmux_cs {
|
||||
+ function = "gpio";
|
||||
+ pins = "gpio12";
|
||||
+ };
|
||||
+ pinconf {
|
||||
+ pins = "gpio13", "gpio14", "gpio15";
|
||||
+ drive-strength = <12>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ pinconf_cs {
|
||||
+ pins = "gpio12";
|
||||
+ drive-strength = <2>;
|
||||
+ bias-disable;
|
||||
+ output-high;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ i2c_0_pins: i2c_0_pinmux {
|
||||
+ pinmux {
|
||||
+ function = "blsp_i2c0";
|
||||
+ pins = "gpio10", "gpio11";
|
||||
+ };
|
||||
+ pinconf {
|
||||
+ pins = "gpio10", "gpio11";
|
||||
+ drive-strength = <16>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ blsp_dma: dma@7884000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ spi_0: spi@78b5000 {
|
||||
+ pinctrl-0 = <&spi_0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "ok";
|
||||
+ cs-gpios = <&tlmm 12 0>;
|
||||
+
|
||||
+ mx25l25635e@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ reg = <0>;
|
||||
+ compatible = "mx25l25635e";
|
||||
+ spi-max-frequency = <24000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
|
||||
+ pinctrl-0 = <&i2c_0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ serial@78af000 {
|
||||
+ pinctrl-0 = <&serial_0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ serial@78b0000 {
|
||||
+ pinctrl-0 = <&serial_1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3: usb3@8af8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2: usb2@60f8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ cryptobam: dma@8e04000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ crypto@8e3a000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ watchdog@b017000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -1,109 +0,0 @@ |
||||
From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Fri, 8 Apr 2016 15:26:10 -0500
|
||||
Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
|
||||
|
||||
v1 was the incorrect choice here and sometimes the board
|
||||
would not come up properly.
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
Changes:
|
||||
- moved L2-Cache to be a subnode of cpu0
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
|
||||
1 file changed, 24 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -34,19 +34,27 @@
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
- enable-method = "qcom,kpss-acc-v1";
|
||||
+ enable-method = "qcom,kpss-acc-v2";
|
||||
+ next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc0>;
|
||||
qcom,saw = <&saw0>;
|
||||
reg = <0x0>;
|
||||
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
||||
clock-frequency = <0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
+
|
||||
+ L2: l2-cache {
|
||||
+ compatible = "qcom,arch-cache";
|
||||
+ cache-level = <2>;
|
||||
+ qcom,saw = <&saw_l2>;
|
||||
+ };
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
- enable-method = "qcom,kpss-acc-v1";
|
||||
+ enable-method = "qcom,kpss-acc-v2";
|
||||
+ next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc1>;
|
||||
qcom,saw = <&saw1>;
|
||||
reg = <0x1>;
|
||||
@@ -58,7 +66,8 @@
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
- enable-method = "qcom,kpss-acc-v1";
|
||||
+ enable-method = "qcom,kpss-acc-v2";
|
||||
+ next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc2>;
|
||||
qcom,saw = <&saw2>;
|
||||
reg = <0x2>;
|
||||
@@ -70,7 +79,8 @@
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
- enable-method = "qcom,kpss-acc-v1";
|
||||
+ enable-method = "qcom,kpss-acc-v2";
|
||||
+ next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc3>;
|
||||
qcom,saw = <&saw3>;
|
||||
reg = <0x3>;
|
||||
@@ -212,22 +222,22 @@
|
||||
};
|
||||
|
||||
acc0: clock-controller@b088000 {
|
||||
- compatible = "qcom,kpss-acc-v1";
|
||||
+ compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
|
||||
};
|
||||
|
||||
acc1: clock-controller@b098000 {
|
||||
- compatible = "qcom,kpss-acc-v1";
|
||||
+ compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
|
||||
};
|
||||
|
||||
acc2: clock-controller@b0a8000 {
|
||||
- compatible = "qcom,kpss-acc-v1";
|
||||
+ compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
|
||||
};
|
||||
|
||||
acc3: clock-controller@b0b8000 {
|
||||
- compatible = "qcom,kpss-acc-v1";
|
||||
+ compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
|
||||
};
|
||||
|
||||
@@ -255,6 +265,12 @@
|
||||
regulator;
|
||||
};
|
||||
|
||||
+ saw_l2: regulator@b012000 {
|
||||
+ compatible = "qcom,saw2";
|
||||
+ reg = <0xb012000 0x1000>;
|
||||
+ regulator;
|
||||
+ };
|
||||
+
|
||||
serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
@ -1,130 +0,0 @@ |
||||
From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Thu, 17 Mar 2016 16:22:28 -0500
|
||||
Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
|
||||
|
||||
This adds the SoC nodes to the ipq4019 device tree and
|
||||
enable it for the DK01.1 board.
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
Changes:
|
||||
- replaced space with tab
|
||||
- added sleep and mock_utmi clocks
|
||||
- added registers for usb2 and usb3 parent node
|
||||
- changed compatible to qca,ipa4019-dwc3
|
||||
- updated usb2 and usb3 names
|
||||
(included the reg - in case they become necessary later)
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++
|
||||
2 files changed, 91 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -108,5 +108,25 @@
|
||||
watchdog@b017000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3: usb3@8af8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2: usb2@60f8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -307,5 +307,76 @@
|
||||
compatible = "qcom,pshold";
|
||||
reg = <0x4ab000 0x4>;
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ compatible = "qca,uni-ssphy";
|
||||
+ reg = <0x9a000 0x800>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
||||
+ reset-names = "por_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ compatible = "qca,baldur-usb3-hsphy";
|
||||
+ reg = <0xa6000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3@8af8800 {
|
||||
+ compatible = "qca,ipq4019-dwc3";
|
||||
+ reg = <0x8af8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB3_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@8a00000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x8a00000 0xf8000>;
|
||||
+ interrupts = <0 132 0>;
|
||||
+ usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ compatible = "qca,baldur-usb2-hsphy";
|
||||
+ reg = <0xa8000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb2@60f8800 {
|
||||
+ compatible = "qca,ipq4019-dwc3";
|
||||
+ reg = <0x60f8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB2_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@6000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x6000000 0xf8000>;
|
||||
+ interrupts = <0 136 0>;
|
||||
+ usb-phy = <&usb2_hs_phy>;
|
||||
+ phy-names = "usb2-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -1,35 +0,0 @@ |
||||
From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sat, 19 Nov 2016 00:58:18 +0100
|
||||
Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
|
||||
|
||||
Add support for the Qualcomm Atheros IPQ4019 SoC.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/Makefile | 1 +
|
||||
arch/arm/mach-qcom/Kconfig | 5 +++++
|
||||
2 files changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/arm/Makefile
|
||||
+++ b/arch/arm/Makefile
|
||||
@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
|
||||
endif
|
||||
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
||||
+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
|
||||
|
||||
# Machine directory name. This list is sorted alphanumerically
|
||||
--- a/arch/arm/mach-qcom/Kconfig
|
||||
+++ b/arch/arm/mach-qcom/Kconfig
|
||||
@@ -28,4 +28,9 @@ config ARCH_MDM9615
|
||||
bool "Enable support for MDM9615"
|
||||
select CLKSRC_QCOM
|
||||
|
||||
+config ARCH_IPQ40XX
|
||||
+ bool "Enable support for IPQ40XX"
|
||||
+ select CLKSRC_QCOM
|
||||
+ select HAVE_ARM_ARCH_TIMER
|
||||
+
|
||||
endif
|
||||
@ -1,105 +0,0 @@ |
||||
From 6091a49b0b06bf838fed80498c4f5f40d0fbd447 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sat, 19 Nov 2016 01:22:46 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add both IPQ4019 wifi block definitions
|
||||
|
||||
The IPQ4019 has two ath10k blocks on the AHB. Both wifi's
|
||||
are already supported by ath10k.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 84 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -378,5 +378,89 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ wifi0: wifi@a000000 {
|
||||
+ compatible = "qcom,ipq4019-wifi";
|
||||
+ reg = <0xa000000 0x200000>;
|
||||
+ resets = <&gcc WIFI0_CPU_INIT_RESET
|
||||
+ &gcc WIFI0_RADIO_SRIF_RESET
|
||||
+ &gcc WIFI0_RADIO_WARM_RESET
|
||||
+ &gcc WIFI0_RADIO_COLD_RESET
|
||||
+ &gcc WIFI0_CORE_WARM_RESET
|
||||
+ &gcc WIFI0_CORE_COLD_RESET>;
|
||||
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
||||
+ "wifi_radio_warm", "wifi_radio_cold",
|
||||
+ "wifi_core_warm", "wifi_core_cold";
|
||||
+ clocks = <&gcc GCC_WCSS2G_CLK
|
||||
+ &gcc GCC_WCSS2G_REF_CLK
|
||||
+ &gcc GCC_WCSS2G_RTC_CLK>;
|
||||
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
||||
+ "wifi_wcss_rtc";
|
||||
+ interrupts = <0 32 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 33 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 34 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 35 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 36 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 37 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 38 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 39 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 40 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 41 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 42 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 43 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 44 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 45 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 46 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 47 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 168 IRQ_TYPE_NONE>;
|
||||
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
+ "msi4", "msi5", "msi6", "msi7",
|
||||
+ "msi8", "msi9", "msi10", "msi11",
|
||||
+ "msi12", "msi13", "msi14", "msi15",
|
||||
+ "legacy";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ wifi1: wifi@a800000 {
|
||||
+ compatible = "qcom,ipq4019-wifi";
|
||||
+ reg = <0xa800000 0x200000>;
|
||||
+ resets = <&gcc WIFI1_CPU_INIT_RESET
|
||||
+ &gcc WIFI1_RADIO_SRIF_RESET
|
||||
+ &gcc WIFI1_RADIO_WARM_RESET
|
||||
+ &gcc WIFI1_RADIO_COLD_RESET
|
||||
+ &gcc WIFI1_CORE_WARM_RESET
|
||||
+ &gcc WIFI1_CORE_COLD_RESET>;
|
||||
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
||||
+ "wifi_radio_warm", "wifi_radio_cold",
|
||||
+ "wifi_core_warm", "wifi_core_cold";
|
||||
+ clocks = <&gcc GCC_WCSS5G_CLK
|
||||
+ &gcc GCC_WCSS5G_REF_CLK
|
||||
+ &gcc GCC_WCSS5G_RTC_CLK>;
|
||||
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
||||
+ "wifi_wcss_rtc";
|
||||
+ interrupts = <0 48 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 49 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 50 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 51 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 52 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 53 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 54 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 55 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 56 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 57 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 58 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 59 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 60 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 61 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 62 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 63 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 169 IRQ_TYPE_NONE>;
|
||||
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
+ "msi4", "msi5", "msi6", "msi7",
|
||||
+ "msi8", "msi9", "msi10", "msi11",
|
||||
+ "msi12", "msi13", "msi14", "msi15",
|
||||
+ "legacy";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -1,29 +0,0 @@ |
||||
From 26fa6fdc627b523277c7a79907233596b2f8a3ef Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sat, 19 Nov 2016 03:29:04 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add pseudo random number generator
|
||||
|
||||
This architecture has a pseudo random number generator
|
||||
supported by the existing "qcom,prng" binding.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -271,6 +271,13 @@
|
||||
regulator;
|
||||
};
|
||||
|
||||
+ rng@22000 {
|
||||
+ compatible = "qcom,prng";
|
||||
+ reg = <0x22000 0x140>;
|
||||
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
||||
+ clock-names = "core";
|
||||
+ };
|
||||
+
|
||||
serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
@ -1,53 +0,0 @@ |
||||
From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
|
||||
From: Rakesh Nair <ranair@codeaurora.org>
|
||||
Date: Wed, 20 Jul 2016 15:02:01 +0530
|
||||
Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
|
||||
netdev_ops
|
||||
|
||||
Add callback support to get default vlan tag and register
|
||||
receive flow steering filter.
|
||||
|
||||
Used by IPQ4019 ess-edma driver.
|
||||
|
||||
BUG=chrome-os-partner:33096
|
||||
TEST=none
|
||||
|
||||
Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
|
||||
Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
|
||||
Reviewed-on: https://chromium-review.googlesource.com/362203
|
||||
Commit-Ready: Grant Grundler <grundler@chromium.org>
|
||||
Tested-by: Grant Grundler <grundler@chromium.org>
|
||||
Reviewed-by: Grant Grundler <grundler@chromium.org>
|
||||
---
|
||||
include/linux/netdevice.h | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/include/linux/netdevice.h
|
||||
+++ b/include/linux/netdevice.h
|
||||
@@ -725,6 +725,16 @@ struct xps_map {
|
||||
#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
|
||||
- sizeof(struct xps_map)) / sizeof(u16))
|
||||
|
||||
+#ifdef CONFIG_RFS_ACCEL
|
||||
+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
|
||||
+ __be32 src,
|
||||
+ __be32 dst,
|
||||
+ __be16 sport,
|
||||
+ __be16 dport,
|
||||
+ u8 proto,
|
||||
+ u16 rxq_index,
|
||||
+ u32 action);
|
||||
+#endif
|
||||
/*
|
||||
* This structure holds all XPS maps for device. Maps are indexed by CPU.
|
||||
*/
|
||||
@@ -1251,6 +1261,9 @@ struct net_device_ops {
|
||||
const struct sk_buff *skb,
|
||||
u16 rxq_index,
|
||||
u32 flow_id);
|
||||
+ int (*ndo_register_rfs_filter)(struct net_device *dev,
|
||||
+ set_rfs_filter_callback_t set_filter);
|
||||
+ int (*ndo_get_default_vlan_tag)(struct net_device *net);
|
||||
#endif
|
||||
int (*ndo_add_slave)(struct net_device *dev,
|
||||
struct net_device *slave_dev);
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,52 +0,0 @@ |
||||
From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 20 Nov 2016 01:10:33 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add mdio node for ethernet
|
||||
|
||||
This patch adds the mdio device-tree node.
|
||||
This is where the switch is connected to, so it's needed
|
||||
for the ethernet interfaces.
|
||||
|
||||
Note: The driver isn't anywhere close to be upstream,
|
||||
so the info might change.
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
|
||||
1 file changed, 28 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -315,6 +315,34 @@
|
||||
reg = <0x4ab000 0x4>;
|
||||
};
|
||||
|
||||
+ mdio@90000 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "qcom,ipq4019-mdio";
|
||||
+ reg = <0x90000 0x64>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ethernet-phy@0 {
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy@2 {
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy@3 {
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy@4 {
|
||||
+ reg = <4>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
compatible = "qca,uni-ssphy";
|
||||
reg = <0x9a000 0x800>;
|
||||
@ -1,46 +0,0 @@ |
||||
From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 20 Nov 2016 02:20:54 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
|
||||
|
||||
This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
|
||||
nodes which are needed for the ar40xx.c driver to initialize the
|
||||
switch.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -343,6 +343,29 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ ess-switch@c000000 {
|
||||
+ compatible = "qcom,ess-switch";
|
||||
+ reg = <0xc000000 0x80000>;
|
||||
+ switch_access_mode = "local bus";
|
||||
+ resets = <&gcc ESS_RESET>;
|
||||
+ reset-names = "ess_rst";
|
||||
+ clocks = <&gcc GCC_ESS_CLK>;
|
||||
+ clock-names = "ess_clk";
|
||||
+ switch_cpu_bmp = <0x1>;
|
||||
+ switch_lan_bmp = <0x1e>;
|
||||
+ switch_wan_bmp = <0x20>;
|
||||
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
|
||||
+ switch_initvlas = <0x7c 0x54>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ess-psgmii@98000 {
|
||||
+ compatible = "qcom,ess-psgmii";
|
||||
+ reg = <0x98000 0x800>;
|
||||
+ psgmii_access_mode = "local bus";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
compatible = "qca,uni-ssphy";
|
||||
reg = <0x9a000 0x800>;
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,92 +0,0 @@ |
||||
From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sun, 20 Nov 2016 01:01:10 +0100
|
||||
Subject: [PATCH] dts: ipq4019: add ethernet essedma node
|
||||
|
||||
This patch adds the device-tree node for the ethernet
|
||||
interfaces.
|
||||
|
||||
Note: The driver isn't anywhere close to be upstream,
|
||||
so the info might change.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 60 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -26,6 +26,8 @@
|
||||
aliases {
|
||||
spi0 = &spi_0;
|
||||
i2c0 = &i2c_0;
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -366,6 +368,64 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ edma@c080000 {
|
||||
+ compatible = "qcom,ess-edma";
|
||||
+ reg = <0xc080000 0x8000>;
|
||||
+ qcom,page-mode = <0>;
|
||||
+ qcom,rx_head_buf_size = <1540>;
|
||||
+ qcom,mdio_supported;
|
||||
+ qcom,poll_required = <1>;
|
||||
+ qcom,num_gmac = <2>;
|
||||
+ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 66 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 67 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 68 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 69 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 70 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 71 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 72 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 73 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 74 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 75 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 76 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 77 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 78 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 79 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 80 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 240 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 241 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 242 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 243 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 244 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 245 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 246 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 247 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 248 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 249 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 250 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 251 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 252 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 253 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 254 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 255 IRQ_TYPE_EDGE_RISING>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ gmac0: gmac0 {
|
||||
+ local-mac-address = [00 00 00 00 00 00];
|
||||
+ vlan_tag = <1 0x1f>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1: gmac1 {
|
||||
+ local-mac-address = [00 00 00 00 00 00];
|
||||
+ qcom,phy_mdio_addr = <4>;
|
||||
+ qcom,poll_required = <1>;
|
||||
+ qcom,forced_speed = <1000>;
|
||||
+ qcom,forced_duplex = <1>;
|
||||
+ vlan_tag = <2 0x20>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
compatible = "qca,uni-ssphy";
|
||||
reg = <0x9a000 0x800>;
|
||||
@ -1,429 +0,0 @@ |
||||
From e73682ec4455c34f3f3edc7f40d90ed297521012 Mon Sep 17 00:00:00 2001
|
||||
From: Senthilkumar N L <snlakshm@codeaurora.org>
|
||||
Date: Tue, 6 Jan 2015 12:52:23 +0530
|
||||
Subject: [PATCH] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
|
||||
|
||||
These drivers handles control and configuration of the HS
|
||||
and SS USB PHY transceivers.
|
||||
|
||||
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
|
||||
---
|
||||
Changed:
|
||||
- replaced spaces with tabs
|
||||
- remove emulation and host variables
|
||||
---
|
||||
drivers/usb/phy/Kconfig | 11 ++
|
||||
drivers/usb/phy/Makefile | 2 +
|
||||
drivers/usb/phy/phy-qca-baldur.c | 233 +++++++++++++++++++++++++++++++++++++++
|
||||
drivers/usb/phy/phy-qca-uniphy.c | 141 +++++++++++++++++++++++
|
||||
4 files changed, 387 insertions(+)
|
||||
create mode 100644 drivers/usb/phy/phy-qca-baldur.c
|
||||
create mode 100644 drivers/usb/phy/phy-qca-uniphy.c
|
||||
|
||||
--- a/drivers/usb/phy/Kconfig
|
||||
+++ b/drivers/usb/phy/Kconfig
|
||||
@@ -195,6 +195,17 @@ config USB_MXS_PHY
|
||||
|
||||
MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
|
||||
|
||||
+config USB_IPQ4019_PHY
|
||||
+ tristate "IPQ4019 PHY wrappers support"
|
||||
+ depends on (USB || USB_GADGET) && ARCH_QCOM
|
||||
+ select USB_PHY
|
||||
+ help
|
||||
+ Enable this to support the USB PHY transceivers on QCA961x chips.
|
||||
+ It handles PHY initialization, clock management required after
|
||||
+ resetting the hardware and power management.
|
||||
+ This driver is required even for peripheral only or host only
|
||||
+ mode configurations.
|
||||
+
|
||||
config USB_ULPI
|
||||
bool "Generic ULPI Transceiver Driver"
|
||||
depends on ARM || ARM64
|
||||
--- a/drivers/usb/phy/Makefile
|
||||
+++ b/drivers/usb/phy/Makefile
|
||||
@@ -21,6 +21,8 @@ obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio
|
||||
obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
|
||||
obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
|
||||
obj-$(CONFIG_USB_QCOM_8X16_PHY) += phy-qcom-8x16-usb.o
|
||||
+obj-$(CONFIG_USB_IPQ4019_PHY) += phy-qca-baldur.o
|
||||
+obj-$(CONFIG_USB_IPQ4019_PHY) += phy-qca-uniphy.o
|
||||
obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
|
||||
obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
|
||||
obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/usb/phy/phy-qca-baldur.c
|
||||
@@ -0,0 +1,233 @@
|
||||
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * Permission to use, copy, modify, and/or distribute this software for any
|
||||
+ * purpose with or without fee is hereby granted, provided that the above
|
||||
+ * copyright notice and this permission notice appear in all copies.
|
||||
+ *
|
||||
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
+#include <linux/usb/phy.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/of_device.h>
|
||||
+
|
||||
+/**
|
||||
+ * USB Hardware registers
|
||||
+ */
|
||||
+#define PHY_CTRL0_ADDR 0x000
|
||||
+#define PHY_CTRL1_ADDR 0x004
|
||||
+#define PHY_CTRL2_ADDR 0x008
|
||||
+#define PHY_CTRL3_ADDR 0x00C
|
||||
+#define PHY_CTRL4_ADDR 0x010
|
||||
+#define PHY_MISC_ADDR 0x024
|
||||
+#define PHY_IPG_ADDR 0x030
|
||||
+
|
||||
+#define PHY_CTRL0_VAL 0xA4600015
|
||||
+#define PHY_CTRL1_VAL 0x09500000
|
||||
+#define PHY_CTRL2_VAL 0x00058180
|
||||
+#define PHY_CTRL3_VAL 0x6DB6DCD6
|
||||
+#define PHY_CTRL4_VAL 0x836DB6DB
|
||||
+#define PHY_MISC_VAL 0x3803FB0C
|
||||
+#define PHY_IPG_VAL 0x47323232
|
||||
+
|
||||
+#define USB30_HS_PHY_HOST_MODE (0x01 << 21)
|
||||
+#define USB20_HS_PHY_HOST_MODE (0x01 << 5)
|
||||
+
|
||||
+/* used to differentiate between USB3 HS and USB2 HS PHY */
|
||||
+struct qca_baldur_hs_data {
|
||||
+ unsigned int usb3_hs_phy;
|
||||
+ unsigned int phy_config_offset;
|
||||
+};
|
||||
+
|
||||
+struct qca_baldur_hs_phy {
|
||||
+ struct device *dev;
|
||||
+ struct usb_phy phy;
|
||||
+
|
||||
+ void __iomem *base;
|
||||
+ void __iomem *qscratch_base;
|
||||
+
|
||||
+ struct reset_control *por_rst;
|
||||
+ struct reset_control *srif_rst;
|
||||
+
|
||||
+ const struct qca_baldur_hs_data *data;
|
||||
+};
|
||||
+
|
||||
+#define phy_to_dw_phy(x) container_of((x), struct qca_baldur_hs_phy, phy)
|
||||
+
|
||||
+static int qca_baldur_phy_read(struct usb_phy *x, u32 reg)
|
||||
+{
|
||||
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
|
||||
+
|
||||
+ return readl(phy->base + reg);
|
||||
+}
|
||||
+
|
||||
+static int qca_baldur_phy_write(struct usb_phy *x, u32 val, u32 reg)
|
||||
+{
|
||||
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
|
||||
+
|
||||
+ writel(val, phy->base + reg);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qca_baldur_hs_phy_init(struct usb_phy *x)
|
||||
+{
|
||||
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
|
||||
+
|
||||
+ /* assert HS PHY POR reset */
|
||||
+ reset_control_assert(phy->por_rst);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ /* assert HS PHY SRIF reset */
|
||||
+ reset_control_assert(phy->srif_rst);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ /* deassert HS PHY SRIF reset and program HS PHY registers */
|
||||
+ reset_control_deassert(phy->srif_rst);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ /* perform PHY register writes */
|
||||
+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
|
||||
+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
|
||||
+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
|
||||
+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
|
||||
+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
|
||||
+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
|
||||
+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
|
||||
+
|
||||
+ msleep(10);
|
||||
+
|
||||
+ /* de-assert USB3 HS PHY POR reset */
|
||||
+ reset_control_deassert(phy->por_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qca_baldur_hs_get_resources(struct qca_baldur_hs_phy *phy)
|
||||
+{
|
||||
+ struct platform_device *pdev = to_platform_device(phy->dev);
|
||||
+ struct resource *res;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ phy->base = devm_ioremap_resource(phy->dev, res);
|
||||
+ if (IS_ERR(phy->base))
|
||||
+ return PTR_ERR(phy->base);
|
||||
+
|
||||
+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
|
||||
+ if (IS_ERR(phy->por_rst))
|
||||
+ return PTR_ERR(phy->por_rst);
|
||||
+
|
||||
+ phy->srif_rst = devm_reset_control_get(phy->dev, "srif_rst");
|
||||
+ if (IS_ERR(phy->srif_rst))
|
||||
+ return PTR_ERR(phy->srif_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void qca_baldur_hs_put_resources(struct qca_baldur_hs_phy *phy)
|
||||
+{
|
||||
+ reset_control_assert(phy->srif_rst);
|
||||
+ reset_control_assert(phy->por_rst);
|
||||
+}
|
||||
+
|
||||
+static int qca_baldur_hs_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct qca_baldur_hs_phy *phy = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ usb_remove_phy(&phy->phy);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void qca_baldur_hs_phy_shutdown(struct usb_phy *x)
|
||||
+{
|
||||
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
|
||||
+
|
||||
+ qca_baldur_hs_put_resources(phy);
|
||||
+}
|
||||
+
|
||||
+static struct usb_phy_io_ops qca_baldur_io_ops = {
|
||||
+ .read = qca_baldur_phy_read,
|
||||
+ .write = qca_baldur_phy_write,
|
||||
+};
|
||||
+
|
||||
+static const struct qca_baldur_hs_data usb3_hs_data = {
|
||||
+ .usb3_hs_phy = 1,
|
||||
+ .phy_config_offset = USB30_HS_PHY_HOST_MODE,
|
||||
+};
|
||||
+
|
||||
+static const struct qca_baldur_hs_data usb2_hs_data = {
|
||||
+ .usb3_hs_phy = 0,
|
||||
+ .phy_config_offset = USB20_HS_PHY_HOST_MODE,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id qca_baldur_hs_id_table[] = {
|
||||
+ { .compatible = "qca,baldur-usb3-hsphy", .data = &usb3_hs_data },
|
||||
+ { .compatible = "qca,baldur-usb2-hsphy", .data = &usb2_hs_data },
|
||||
+ { /* Sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, qca_baldur_hs_id_table);
|
||||
+
|
||||
+static int qca_baldur_hs_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ const struct of_device_id *match;
|
||||
+ struct qca_baldur_hs_phy *phy;
|
||||
+ int err;
|
||||
+
|
||||
+ match = of_match_device(qca_baldur_hs_id_table, &pdev->dev);
|
||||
+ if (!match)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
|
||||
+ if (!phy)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ platform_set_drvdata(pdev, phy);
|
||||
+ phy->dev = &pdev->dev;
|
||||
+
|
||||
+ phy->data = match->data;
|
||||
+
|
||||
+ err = qca_baldur_hs_get_resources(phy);
|
||||
+ if (err < 0) {
|
||||
+ dev_err(&pdev->dev, "failed to request resources: %d\n", err);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ phy->phy.dev = phy->dev;
|
||||
+ phy->phy.label = "qca-baldur-hsphy";
|
||||
+ phy->phy.init = qca_baldur_hs_phy_init;
|
||||
+ phy->phy.shutdown = qca_baldur_hs_phy_shutdown;
|
||||
+ phy->phy.type = USB_PHY_TYPE_USB2;
|
||||
+ phy->phy.io_ops = &qca_baldur_io_ops;
|
||||
+
|
||||
+ err = usb_add_phy_dev(&phy->phy);
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver qca_baldur_hs_driver = {
|
||||
+ .probe = qca_baldur_hs_probe,
|
||||
+ .remove = qca_baldur_hs_remove,
|
||||
+ .driver = {
|
||||
+ .name = "qca-baldur-hsphy",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = qca_baldur_hs_id_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(qca_baldur_hs_driver);
|
||||
+
|
||||
+MODULE_ALIAS("platform:qca-baldur-hsphy");
|
||||
+MODULE_LICENSE("Dual BSD/GPL");
|
||||
+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
|
||||
--- /dev/null
|
||||
+++ b/drivers/usb/phy/phy-qca-uniphy.c
|
||||
@@ -0,0 +1,135 @@
|
||||
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * Permission to use, copy, modify, and/or distribute this software for any
|
||||
+ * purpose with or without fee is hereby granted, provided that the above
|
||||
+ * copyright notice and this permission notice appear in all copies.
|
||||
+ *
|
||||
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
+#include <linux/usb/phy.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/of_device.h>
|
||||
+
|
||||
+struct qca_uni_ss_phy {
|
||||
+ struct usb_phy phy;
|
||||
+ struct device *dev;
|
||||
+
|
||||
+ void __iomem *base;
|
||||
+
|
||||
+ struct reset_control *por_rst;
|
||||
+};
|
||||
+
|
||||
+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_ss_phy, phy)
|
||||
+
|
||||
+static void qca_uni_ss_phy_shutdown(struct usb_phy *x)
|
||||
+{
|
||||
+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
|
||||
+
|
||||
+ /* assert SS PHY POR reset */
|
||||
+ reset_control_assert(phy->por_rst);
|
||||
+}
|
||||
+
|
||||
+static int qca_uni_ss_phy_init(struct usb_phy *x)
|
||||
+{
|
||||
+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
|
||||
+
|
||||
+ /* assert SS PHY POR reset */
|
||||
+ reset_control_assert(phy->por_rst);
|
||||
+
|
||||
+ msleep(20);
|
||||
+
|
||||
+ /* deassert SS PHY POR reset */
|
||||
+ reset_control_deassert(phy->por_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qca_uni_ss_get_resources(struct platform_device *pdev,
|
||||
+ struct qca_uni_ss_phy *phy)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ phy->base = devm_ioremap_resource(phy->dev, res);
|
||||
+ if (IS_ERR(phy->base))
|
||||
+ return PTR_ERR(phy->base);
|
||||
+
|
||||
+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
|
||||
+ if (IS_ERR(phy->por_rst))
|
||||
+ return PTR_ERR(phy->por_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qca_uni_ss_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct qca_uni_ss_phy *phy = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ usb_remove_phy(&phy->phy);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id qca_uni_ss_id_table[] = {
|
||||
+ { .compatible = "qca,uni-ssphy" },
|
||||
+ { /* Sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, qca_uni_ss_id_table);
|
||||
+
|
||||
+static int qca_uni_ss_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct qca_uni_ss_phy *phy;
|
||||
+ int ret;
|
||||
+
|
||||
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
|
||||
+ if (!phy)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ platform_set_drvdata(pdev, phy);
|
||||
+ phy->dev = &pdev->dev;
|
||||
+
|
||||
+ ret = qca_uni_ss_get_resources(pdev, phy);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ phy->phy.dev = phy->dev;
|
||||
+ phy->phy.label = "qca-uni-ssphy";
|
||||
+ phy->phy.init = qca_uni_ss_phy_init;
|
||||
+ phy->phy.shutdown = qca_uni_ss_phy_shutdown;
|
||||
+ phy->phy.type = USB_PHY_TYPE_USB3;
|
||||
+
|
||||
+ ret = usb_add_phy_dev(&phy->phy);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver qca_uni_ss_driver = {
|
||||
+ .probe = qca_uni_ss_probe,
|
||||
+ .remove = qca_uni_ss_remove,
|
||||
+ .driver = {
|
||||
+ .name = "qca-uni-ssphy",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = qca_uni_ss_id_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(qca_uni_ss_driver);
|
||||
+
|
||||
+MODULE_ALIAS("platform:qca-uni-ssphy");
|
||||
+MODULE_LICENSE("Dual BSD/GPL");
|
||||
+MODULE_DESCRIPTION("USB3 QCA UNI SSPHY driver");
|
||||
@ -1,25 +0,0 @@ |
||||
From 08c18ab774368feb610d1eb952957bb1bb35129f Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sat, 19 Nov 2016 00:52:35 +0100
|
||||
Subject: [PATCH 37/38] usb: dwc3: register qca,ipq4019-dwc3 in dwc3-of-simple
|
||||
|
||||
For host mode, the dwc3 found in the IPQ4019 can be driven
|
||||
by the dwc3-of-simple module. It will get more tricky for
|
||||
OTG since they'll need to enable VBUS and reconfigure the
|
||||
registers.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
@@ -199,6 +199,7 @@ static const struct dev_pm_ops dwc3_of_s
|
||||
|
||||
static const struct of_device_id of_dwc3_simple_match[] = {
|
||||
{ .compatible = "qcom,dwc3" },
|
||||
+ { .compatible = "qca,ipq4019-dwc3" },
|
||||
{ .compatible = "rockchip,rk3399-dwc3" },
|
||||
{ .compatible = "xlnx,zynqmp-dwc3" },
|
||||
{ .compatible = "cavium,octeon-7130-usb-uctl" },
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,236 +0,0 @@ |
||||
From e77af7de404eb464f7da9e0daeb8b362cc66a7ba Mon Sep 17 00:00:00 2001
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Tue, 9 May 2017 11:45:00 +0530
|
||||
Subject: [PATCH] msm: pinctrl: Add support to configure ipq40xx GPIO_PULL bits
|
||||
|
||||
GPIO_PULL bits configurations in TLMM_GPIO_CFG register
|
||||
differs for IPQ40xx from rest of the other qcom SoC's.
|
||||
This change add support to configure the msm_gpio_pull
|
||||
bits for ipq40xx, It is required to fix the proper
|
||||
configurations of gpio-pull bits for nand pins mux.
|
||||
|
||||
IPQ40xx SoC:
|
||||
2'b10: Internal pull up enable.
|
||||
2'b11: Unsupport
|
||||
|
||||
For other SoC's:
|
||||
2'b10: Keeper
|
||||
2'b11: Pull-Up
|
||||
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
---
|
||||
drivers/pinctrl/qcom/pinctrl-apq8064.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-apq8084.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 8 ++++++++
|
||||
drivers/pinctrl/qcom/pinctrl-ipq8064.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-mdm9615.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm.c | 21 ++++++++-------------
|
||||
drivers/pinctrl/qcom/pinctrl-msm.h | 19 +++++++++++++++++++
|
||||
drivers/pinctrl/qcom/pinctrl-msm8660.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm8916.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm8960.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm8x74.c | 1 +
|
||||
11 files changed, 43 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
|
||||
@@ -597,6 +597,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = apq8064_groups,
|
||||
.ngroups = ARRAY_SIZE(apq8064_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int apq8064_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
|
||||
@@ -1206,6 +1206,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = apq8084_groups,
|
||||
.ngroups = ARRAY_SIZE(apq8084_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int apq8084_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
@@ -1531,6 +1531,13 @@ static const struct msm_pingroup ipq4019
|
||||
PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
};
|
||||
|
||||
+static const struct msm_pinctrl_gpio_pull ipq4019_gpio_pull = {
|
||||
+ .no_pull = 0,
|
||||
+ .pull_down = 1,
|
||||
+ .keeper = 0,
|
||||
+ .pull_up = 2,
|
||||
+};
|
||||
+
|
||||
static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
|
||||
.pins = ipq4019_pins,
|
||||
.npins = ARRAY_SIZE(ipq4019_pins),
|
||||
@@ -1539,6 +1546,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = ipq4019_groups,
|
||||
.ngroups = ARRAY_SIZE(ipq4019_groups),
|
||||
.ngpios = 100,
|
||||
+ .gpio_pull = &ipq4019_gpio_pull,
|
||||
};
|
||||
|
||||
static int ipq4019_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
|
||||
@@ -630,6 +630,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = ipq8064_groups,
|
||||
.ngroups = ARRAY_SIZE(ipq8064_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int ipq8064_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
|
||||
@@ -444,6 +444,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = mdm9615_groups,
|
||||
.ngroups = ARRAY_SIZE(mdm9615_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int mdm9615_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
@@ -203,11 +203,6 @@ static int msm_config_reg(struct msm_pin
|
||||
return 0;
|
||||
}
|
||||
|
||||
-#define MSM_NO_PULL 0
|
||||
-#define MSM_PULL_DOWN 1
|
||||
-#define MSM_KEEPER 2
|
||||
-#define MSM_PULL_UP 3
|
||||
-
|
||||
static unsigned msm_regval_to_drive(u32 val)
|
||||
{
|
||||
return (val + 1) * 2;
|
||||
@@ -238,16 +233,16 @@ static int msm_config_group_get(struct p
|
||||
/* Convert register value to pinconf value */
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
- arg = arg == MSM_NO_PULL;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->no_pull;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
- arg = arg == MSM_PULL_DOWN;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->pull_down;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_BUS_HOLD:
|
||||
- arg = arg == MSM_KEEPER;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->keeper;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
- arg = arg == MSM_PULL_UP;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->pull_up;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
arg = msm_regval_to_drive(arg);
|
||||
@@ -304,16 +299,16 @@ static int msm_config_group_set(struct p
|
||||
/* Convert pinconf values to register values */
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
- arg = MSM_NO_PULL;
|
||||
+ arg = pctrl->soc->gpio_pull->no_pull;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
- arg = MSM_PULL_DOWN;
|
||||
+ arg = pctrl->soc->gpio_pull->pull_down;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_BUS_HOLD:
|
||||
- arg = MSM_KEEPER;
|
||||
+ arg = pctrl->soc->gpio_pull->keeper;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
- arg = MSM_PULL_UP;
|
||||
+ arg = pctrl->soc->gpio_pull->pull_up;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
/* Check for invalid values */
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
|
||||
@@ -98,6 +98,16 @@ struct msm_pingroup {
|
||||
};
|
||||
|
||||
/**
|
||||
+ * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor
|
||||
+ */
|
||||
+struct msm_pinctrl_gpio_pull {
|
||||
+ unsigned no_pull;
|
||||
+ unsigned pull_down;
|
||||
+ unsigned keeper;
|
||||
+ unsigned pull_up;
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
|
||||
* @pins: An array describing all pins the pin controller affects.
|
||||
* @npins: The number of entries in @pins.
|
||||
@@ -106,6 +116,7 @@ struct msm_pingroup {
|
||||
* @groups: An array describing all pin groups the pin SoC supports.
|
||||
* @ngroups: The numbmer of entries in @groups.
|
||||
* @ngpio: The number of pingroups the driver should expose as GPIOs.
|
||||
+ * @gpio_pull_val: The pull value bit field descriptor.
|
||||
*/
|
||||
struct msm_pinctrl_soc_data {
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
@@ -115,6 +126,14 @@ struct msm_pinctrl_soc_data {
|
||||
const struct msm_pingroup *groups;
|
||||
unsigned ngroups;
|
||||
unsigned ngpios;
|
||||
+ const struct msm_pinctrl_gpio_pull *gpio_pull;
|
||||
+};
|
||||
+
|
||||
+static const struct msm_pinctrl_gpio_pull msm_gpio_pull = {
|
||||
+ .no_pull = 0,
|
||||
+ .pull_down = 1,
|
||||
+ .keeper = 2,
|
||||
+ .pull_up = 3,
|
||||
};
|
||||
|
||||
int msm_pinctrl_probe(struct platform_device *pdev,
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
|
||||
@@ -979,6 +979,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8660_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8660_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8660_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
|
||||
@@ -967,6 +967,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8916_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8916_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8916_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
|
||||
@@ -1244,6 +1244,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8960_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8960_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8960_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
|
||||
@@ -1069,6 +1069,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8x74_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8x74_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8x74_pinctrl_probe(struct platform_device *pdev)
|
||||
@ -1,370 +0,0 @@ |
||||
From 074036f9de6b8c5fc642e8e2540950f6a35aa804 Mon Sep 17 00:00:00 2001
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Thu, 20 Apr 2017 10:31:10 +0530
|
||||
Subject: [PATCH] qcom: mtd: nand: Add bam_dma support in qcom_nand driver
|
||||
|
||||
The current driver only support ADM DMA so this patch adds the
|
||||
BAM DMA support in current NAND driver with compatible string
|
||||
qcom,ebi2-nandc-bam.
|
||||
Added bam channels and data buffers, NAND BAM uses 3 channels:
|
||||
command, data tx and data rx, while ADM uses only single channel.
|
||||
So this patch adds the BAM channel in device tree and using the
|
||||
same in NAND driver allocation function.
|
||||
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
---
|
||||
.../devicetree/bindings/mtd/qcom_nandc.txt | 69 +++++++--
|
||||
drivers/mtd/nand/qcom_nandc.c | 160 +++++++++++++++++----
|
||||
2 files changed, 190 insertions(+), 39 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
|
||||
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
|
||||
@@ -1,21 +1,26 @@
|
||||
* Qualcomm NAND controller
|
||||
|
||||
Required properties:
|
||||
-- compatible: should be "qcom,ipq806x-nand"
|
||||
+- compatible: "qcom,ipq806x-nand" for IPQ8064 which uses
|
||||
+ ADM DMA.
|
||||
+ "qcom,ebi2-nand-bam" - nand drivers using BAM DMA
|
||||
+ like IPQ4019.
|
||||
- reg: MMIO address range
|
||||
- clocks: must contain core clock and always on clock
|
||||
- clock-names: must contain "core" for the core clock and "aon" for the
|
||||
always on clock
|
||||
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
|
||||
- controller node and the channel number to be used for
|
||||
- NAND. Refer to dma.txt and qcom_adm.txt for more details
|
||||
-- dma-names: must be "rxtx"
|
||||
-- qcom,cmd-crci: must contain the ADM command type CRCI block instance
|
||||
- number specified for the NAND controller on the given
|
||||
- platform
|
||||
-- qcom,data-crci: must contain the ADM data type CRCI block instance
|
||||
- number specified for the NAND controller on the given
|
||||
- platform
|
||||
+ or BAM DMA controller node and the channel number to
|
||||
+ be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
|
||||
+ and qcom_bam_dma.txt(BAM) for more details
|
||||
+- dma-names: "rxtx" - ADM
|
||||
+ "tx", "rx", "cmd" - BAM
|
||||
+- qcom,cmd-crci: Only required for ADM DMA. must contain the ADM command
|
||||
+ type CRCI block instance number specified for the NAND
|
||||
+ controller on the given platform.
|
||||
+- qcom,data-crci: Only required for ADM DMA. must contain the ADM data
|
||||
+ type CRCI block instance number specified for the NAND
|
||||
+ controller on the given platform.
|
||||
- #address-cells: <1> - subnodes give the chip-select number
|
||||
- #size-cells: <0>
|
||||
|
||||
@@ -44,7 +49,7 @@ partition.txt for more detail.
|
||||
Example:
|
||||
|
||||
nand@1ac00000 {
|
||||
- compatible = "qcom,ebi2-nandc";
|
||||
+ compatible = "qcom,ipq806x-nand","qcom.qcom_nand";
|
||||
reg = <0x1ac00000 0x800>;
|
||||
|
||||
clocks = <&gcc EBI2_CLK>,
|
||||
@@ -58,6 +63,48 @@ nand@1ac00000 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+
|
||||
+ nandcs@0 {
|
||||
+ compatible = "qcom,nandcs";
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ nand-ecc-strength = <4>;
|
||||
+ nand-ecc-step-size = <512>;
|
||||
+ nand-bus-width = <8>;
|
||||
+
|
||||
+ partitions {
|
||||
+ compatible = "fixed-partitions";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "boot-nand";
|
||||
+ reg = <0 0x58a0000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@58a0000 {
|
||||
+ label = "fs-nand";
|
||||
+ reg = <0x58a0000 0x4000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+nand@79B0000 {
|
||||
+ compatible = "qcom,ebi2-nandc-bam";
|
||||
+ reg = <0x79B0000 0x1000>;
|
||||
+
|
||||
+ clocks = <&gcc EBI2_CLK>,
|
||||
+ <&gcc EBI2_AON_CLK>;
|
||||
+ clock-names = "core", "aon";
|
||||
+
|
||||
+ dmas = <&qpicbam 0>,
|
||||
+ <&qpicbam 1>,
|
||||
+ <&qpicbam 2>;
|
||||
+ dma-names = "tx", "rx", "cmd";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
|
||||
nandcs@0 {
|
||||
compatible = "qcom,nandcs";
|
||||
--- a/drivers/mtd/nand/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/qcom_nandc.c
|
||||
@@ -234,6 +234,7 @@ struct nandc_regs {
|
||||
* by upper layers directly
|
||||
* @buf_size/count/start: markers for chip->read_buf/write_buf functions
|
||||
* @reg_read_buf: local buffer for reading back registers via DMA
|
||||
+ * @reg_read_buf_phys: contains dma address for register read buffer
|
||||
* @reg_read_pos: marker for data read in reg_read_buf
|
||||
*
|
||||
* @regs: a contiguous chunk of memory for DMA register
|
||||
@@ -242,7 +243,10 @@ struct nandc_regs {
|
||||
* @cmd1/vld: some fixed controller register values
|
||||
* @ecc_modes: supported ECC modes by the current controller,
|
||||
* initialized via DT match data
|
||||
- */
|
||||
+ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
|
||||
+ * @dma_bam_enabled: flag to tell whether nand controller is using
|
||||
+ * bam dma
|
||||
+*/
|
||||
struct qcom_nand_controller {
|
||||
struct nand_hw_control controller;
|
||||
struct list_head host_list;
|
||||
@@ -255,17 +259,28 @@ struct qcom_nand_controller {
|
||||
struct clk *core_clk;
|
||||
struct clk *aon_clk;
|
||||
|
||||
- struct dma_chan *chan;
|
||||
- unsigned int cmd_crci;
|
||||
- unsigned int data_crci;
|
||||
struct list_head desc_list;
|
||||
+ union {
|
||||
+ struct {
|
||||
+ struct dma_chan *tx_chan;
|
||||
+ struct dma_chan *rx_chan;
|
||||
+ struct dma_chan *cmd_chan;
|
||||
+ };
|
||||
+ struct {
|
||||
+ struct dma_chan *chan;
|
||||
+ unsigned int cmd_crci;
|
||||
+ unsigned int data_crci;
|
||||
+ };
|
||||
+ };
|
||||
|
||||
u8 *data_buffer;
|
||||
+ bool dma_bam_enabled;
|
||||
int buf_size;
|
||||
int buf_count;
|
||||
int buf_start;
|
||||
|
||||
__le32 *reg_read_buf;
|
||||
+ dma_addr_t reg_read_buf_phys;
|
||||
int reg_read_pos;
|
||||
|
||||
struct nandc_regs *regs;
|
||||
@@ -324,6 +339,17 @@ struct qcom_nand_host {
|
||||
u32 clrreadstatus;
|
||||
};
|
||||
|
||||
+/*
|
||||
+ * This data type corresponds to the nand driver data which will be used at
|
||||
+ * driver probe time
|
||||
+ * @ecc_modes - ecc mode for nand
|
||||
+ * @dma_bam_enabled - whether this driver is using bam
|
||||
+ */
|
||||
+struct qcom_nand_driver_data {
|
||||
+ u32 ecc_modes;
|
||||
+ bool dma_bam_enabled;
|
||||
+};
|
||||
+
|
||||
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct qcom_nand_host, chip);
|
||||
@@ -1949,16 +1975,46 @@ static int qcom_nandc_alloc(struct qcom_
|
||||
if (!nandc->regs)
|
||||
return -ENOMEM;
|
||||
|
||||
- nandc->reg_read_buf = devm_kzalloc(nandc->dev,
|
||||
- MAX_REG_RD * sizeof(*nandc->reg_read_buf),
|
||||
- GFP_KERNEL);
|
||||
- if (!nandc->reg_read_buf)
|
||||
- return -ENOMEM;
|
||||
+ if (!nandc->dma_bam_enabled) {
|
||||
+ nandc->reg_read_buf = devm_kzalloc(nandc->dev,
|
||||
+ MAX_REG_RD *
|
||||
+ sizeof(*nandc->reg_read_buf),
|
||||
+ GFP_KERNEL);
|
||||
|
||||
- nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
|
||||
- if (!nandc->chan) {
|
||||
- dev_err(nandc->dev, "failed to request slave channel\n");
|
||||
- return -ENODEV;
|
||||
+ if (!nandc->reg_read_buf)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
|
||||
+ if (!nandc->chan) {
|
||||
+ dev_err(nandc->dev, "failed to request slave channel\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ } else {
|
||||
+ nandc->reg_read_buf = dmam_alloc_coherent(nandc->dev,
|
||||
+ MAX_REG_RD *
|
||||
+ sizeof(*nandc->reg_read_buf),
|
||||
+ &nandc->reg_read_buf_phys, GFP_KERNEL);
|
||||
+
|
||||
+ if (!nandc->reg_read_buf)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
|
||||
+ if (!nandc->tx_chan) {
|
||||
+ dev_err(nandc->dev, "failed to request tx channel\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
|
||||
+ if (!nandc->rx_chan) {
|
||||
+ dev_err(nandc->dev, "failed to request rx channel\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
|
||||
+ if (!nandc->cmd_chan) {
|
||||
+ dev_err(nandc->dev, "failed to request cmd channel\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&nandc->desc_list);
|
||||
@@ -1971,8 +2027,35 @@ static int qcom_nandc_alloc(struct qcom_
|
||||
|
||||
static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
|
||||
{
|
||||
- dma_release_channel(nandc->chan);
|
||||
-}
|
||||
+ if (nandc->dma_bam_enabled) {
|
||||
+ if (nandc->tx_chan)
|
||||
+ dma_release_channel(nandc->tx_chan);
|
||||
+
|
||||
+ if (nandc->rx_chan)
|
||||
+ dma_release_channel(nandc->rx_chan);
|
||||
+
|
||||
+ if (nandc->cmd_chan)
|
||||
+ dma_release_channel(nandc->tx_chan);
|
||||
+
|
||||
+ if (nandc->reg_read_buf)
|
||||
+ dmam_free_coherent(nandc->dev, MAX_REG_RD *
|
||||
+ sizeof(*nandc->reg_read_buf),
|
||||
+ nandc->reg_read_buf,
|
||||
+ nandc->reg_read_buf_phys);
|
||||
+ } else {
|
||||
+ if (nandc->chan)
|
||||
+ dma_release_channel(nandc->chan);
|
||||
+
|
||||
+ if (nandc->reg_read_buf)
|
||||
+ devm_kfree(nandc->dev, nandc->reg_read_buf);
|
||||
+ }
|
||||
+
|
||||
+ if (nandc->regs)
|
||||
+ devm_kfree(nandc->dev, nandc->regs);
|
||||
+
|
||||
+ if (nandc->data_buffer)
|
||||
+ devm_kfree(nandc->dev, nandc->data_buffer);
|
||||
+ }
|
||||
|
||||
/* one time setup of a few nand controller registers */
|
||||
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
|
||||
@@ -2010,6 +2093,8 @@ static int qcom_nand_host_init(struct qc
|
||||
mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
|
||||
mtd->owner = THIS_MODULE;
|
||||
mtd->dev.parent = dev;
|
||||
+ mtd->priv = chip;
|
||||
+ chip->priv = nandc;
|
||||
|
||||
chip->cmdfunc = qcom_nandc_command;
|
||||
chip->select_chip = qcom_nandc_select_chip;
|
||||
@@ -2057,16 +2142,20 @@ static int qcom_nandc_parse_dt(struct pl
|
||||
struct device_node *np = nandc->dev->of_node;
|
||||
int ret;
|
||||
|
||||
- ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
|
||||
- if (ret) {
|
||||
- dev_err(nandc->dev, "command CRCI unspecified\n");
|
||||
- return ret;
|
||||
- }
|
||||
+ if (!nandc->dma_bam_enabled) {
|
||||
+ ret = of_property_read_u32(np, "qcom,cmd-crci",
|
||||
+ &nandc->cmd_crci);
|
||||
+ if (ret) {
|
||||
+ dev_err(nandc->dev, "command CRCI unspecified\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
|
||||
- ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
|
||||
- if (ret) {
|
||||
- dev_err(nandc->dev, "data CRCI unspecified\n");
|
||||
- return ret;
|
||||
+ ret = of_property_read_u32(np, "qcom,data-crci",
|
||||
+ &nandc->data_crci);
|
||||
+ if (ret) {
|
||||
+ dev_err(nandc->dev, "data CRCI unspecified\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -2081,6 +2170,7 @@ static int qcom_nandc_probe(struct platf
|
||||
struct device_node *dn = dev->of_node, *child;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
+ struct qcom_nand_driver_data *driver_data;
|
||||
|
||||
nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
|
||||
if (!nandc)
|
||||
@@ -2095,7 +2185,10 @@ static int qcom_nandc_probe(struct platf
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
- nandc->ecc_modes = (unsigned long)dev_data;
|
||||
+ driver_data = (struct qcom_nand_driver_data *)dev_data;
|
||||
+
|
||||
+ nandc->ecc_modes = driver_data->ecc_modes;
|
||||
+ nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
nandc->base = devm_ioremap_resource(dev, res);
|
||||
@@ -2187,7 +2280,15 @@ static int qcom_nandc_remove(struct plat
|
||||
return 0;
|
||||
}
|
||||
|
||||
-#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
|
||||
+struct qcom_nand_driver_data ebi2_nandc_bam_data = {
|
||||
+ .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
|
||||
+ .dma_bam_enabled = true,
|
||||
+};
|
||||
+
|
||||
+struct qcom_nand_driver_data ebi2_nandc_data = {
|
||||
+ .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
|
||||
+ .dma_bam_enabled = false,
|
||||
+};
|
||||
|
||||
/*
|
||||
* data will hold a struct pointer containing more differences once we support
|
||||
@@ -2195,7 +2296,10 @@ static int qcom_nandc_remove(struct plat
|
||||
*/
|
||||
static const struct of_device_id qcom_nandc_of_match[] = {
|
||||
{ .compatible = "qcom,ipq806x-nand",
|
||||
- .data = (void *)EBI2_NANDC_ECC_MODES,
|
||||
+ .data = (void *) &ebi2_nandc_data,
|
||||
+ },
|
||||
+ { .compatible = "qcom,ebi2-nandc-bam",
|
||||
+ .data = (void *) &ebi2_nandc_bam_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,209 +0,0 @@ |
||||
From 5a7ccdf845d64b385affdcffaf2defbe9848be15 Mon Sep 17 00:00:00 2001
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Thu, 20 Apr 2017 10:39:00 +0530
|
||||
Subject: [PATCH] dmaengine: qcom: bam_dma: Add custom data mapping
|
||||
|
||||
Add a new function to support for preparing DMA descriptor
|
||||
for custom data.
|
||||
|
||||
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
---
|
||||
drivers/dma/qcom/bam_dma.c | 97 +++++++++++++++++++++++++++++++++++++---
|
||||
include/linux/dma/qcom_bam_dma.h | 14 ++++++
|
||||
include/linux/dmaengine.h | 14 ++++++
|
||||
3 files changed, 119 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/dma/qcom/bam_dma.c
|
||||
+++ b/drivers/dma/qcom/bam_dma.c
|
||||
@@ -49,6 +49,7 @@
|
||||
#include <linux/clk.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
+#include <linux/dma/qcom_bam_dma.h>
|
||||
|
||||
#include "../dmaengine.h"
|
||||
#include "../virt-dma.h"
|
||||
@@ -61,11 +62,6 @@ struct bam_desc_hw {
|
||||
|
||||
#define BAM_DMA_AUTOSUSPEND_DELAY 100
|
||||
|
||||
-#define DESC_FLAG_INT BIT(15)
|
||||
-#define DESC_FLAG_EOT BIT(14)
|
||||
-#define DESC_FLAG_EOB BIT(13)
|
||||
-#define DESC_FLAG_NWD BIT(12)
|
||||
-
|
||||
struct bam_async_desc {
|
||||
struct virt_dma_desc vd;
|
||||
|
||||
@@ -670,6 +666,93 @@ err_out:
|
||||
}
|
||||
|
||||
/**
|
||||
+ * bam_prep_dma_custom_mapping - Prep DMA descriptor from custom data
|
||||
+ *
|
||||
+ * @chan: dma channel
|
||||
+ * @data: custom data
|
||||
+ * @flags: DMA flags
|
||||
+ */
|
||||
+static struct dma_async_tx_descriptor *bam_prep_dma_custom_mapping(
|
||||
+ struct dma_chan *chan,
|
||||
+ void *data, unsigned long flags)
|
||||
+{
|
||||
+ struct bam_chan *bchan = to_bam_chan(chan);
|
||||
+ struct bam_device *bdev = bchan->bdev;
|
||||
+ struct bam_async_desc *async_desc;
|
||||
+ struct qcom_bam_custom_data *desc_data = data;
|
||||
+ u32 i;
|
||||
+ struct bam_desc_hw *desc;
|
||||
+ unsigned int num_alloc = 0;
|
||||
+
|
||||
+
|
||||
+ if (!is_slave_direction(desc_data->dir)) {
|
||||
+ dev_err(bdev->dev, "invalid dma direction\n");
|
||||
+ return NULL;
|
||||
+ }
|
||||
+
|
||||
+ /* calculate number of required entries */
|
||||
+ for (i = 0; i < desc_data->sgl_cnt; i++)
|
||||
+ num_alloc += DIV_ROUND_UP(
|
||||
+ sg_dma_len(&desc_data->bam_sgl[i].sgl), BAM_FIFO_SIZE);
|
||||
+
|
||||
+ /* allocate enough room to accommodate the number of entries */
|
||||
+ async_desc = kzalloc(sizeof(*async_desc) +
|
||||
+ (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
|
||||
+
|
||||
+ if (!async_desc)
|
||||
+ goto err_out;
|
||||
+
|
||||
+ if (flags & DMA_PREP_FENCE)
|
||||
+ async_desc->flags |= DESC_FLAG_NWD;
|
||||
+
|
||||
+ if (flags & DMA_PREP_INTERRUPT)
|
||||
+ async_desc->flags |= DESC_FLAG_EOT;
|
||||
+ else
|
||||
+ async_desc->flags |= DESC_FLAG_INT;
|
||||
+
|
||||
+ async_desc->num_desc = num_alloc;
|
||||
+ async_desc->curr_desc = async_desc->desc;
|
||||
+ async_desc->dir = desc_data->dir;
|
||||
+
|
||||
+ /* fill in temporary descriptors */
|
||||
+ desc = async_desc->desc;
|
||||
+ for (i = 0; i < desc_data->sgl_cnt; i++) {
|
||||
+ unsigned int remainder;
|
||||
+ unsigned int curr_offset = 0;
|
||||
+
|
||||
+ remainder = sg_dma_len(&desc_data->bam_sgl[i].sgl);
|
||||
+
|
||||
+ do {
|
||||
+ desc->addr = cpu_to_le32(
|
||||
+ sg_dma_address(&desc_data->bam_sgl[i].sgl) +
|
||||
+ curr_offset);
|
||||
+
|
||||
+ if (desc_data->bam_sgl[i].dma_flags)
|
||||
+ desc->flags |= cpu_to_le16(
|
||||
+ desc_data->bam_sgl[i].dma_flags);
|
||||
+
|
||||
+ if (remainder > BAM_FIFO_SIZE) {
|
||||
+ desc->size = cpu_to_le16(BAM_FIFO_SIZE);
|
||||
+ remainder -= BAM_FIFO_SIZE;
|
||||
+ curr_offset += BAM_FIFO_SIZE;
|
||||
+ } else {
|
||||
+ desc->size = cpu_to_le16(remainder);
|
||||
+ remainder = 0;
|
||||
+ }
|
||||
+
|
||||
+ async_desc->length += desc->size;
|
||||
+ desc++;
|
||||
+ } while (remainder > 0);
|
||||
+ }
|
||||
+
|
||||
+ return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
|
||||
+
|
||||
+err_out:
|
||||
+ kfree(async_desc);
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
* bam_dma_terminate_all - terminate all transactions on a channel
|
||||
* @bchan: bam dma channel
|
||||
*
|
||||
@@ -960,7 +1043,7 @@ static void bam_start_dma(struct bam_cha
|
||||
|
||||
/* set any special flags on the last descriptor */
|
||||
if (async_desc->num_desc == async_desc->xfer_len)
|
||||
- desc[async_desc->xfer_len - 1].flags =
|
||||
+ desc[async_desc->xfer_len - 1].flags |=
|
||||
cpu_to_le16(async_desc->flags);
|
||||
else
|
||||
desc[async_desc->xfer_len - 1].flags |=
|
||||
@@ -1237,6 +1320,8 @@ static int bam_dma_probe(struct platform
|
||||
bdev->common.device_alloc_chan_resources = bam_alloc_chan;
|
||||
bdev->common.device_free_chan_resources = bam_free_chan;
|
||||
bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
|
||||
+ bdev->common.device_prep_dma_custom_mapping =
|
||||
+ bam_prep_dma_custom_mapping;
|
||||
bdev->common.device_config = bam_slave_config;
|
||||
bdev->common.device_pause = bam_pause;
|
||||
bdev->common.device_resume = bam_resume;
|
||||
--- a/include/linux/dma/qcom_bam_dma.h
|
||||
+++ b/include/linux/dma/qcom_bam_dma.h
|
||||
@@ -65,6 +65,19 @@ enum bam_command_type {
|
||||
};
|
||||
|
||||
/*
|
||||
+ * QCOM BAM DMA custom data
|
||||
+ *
|
||||
+ * @sgl_cnt: number of sgl in bam_sgl
|
||||
+ * @dir: DMA data transfer direction
|
||||
+ * @bam_sgl: BAM SGL pointer
|
||||
+ */
|
||||
+struct qcom_bam_custom_data {
|
||||
+ u32 sgl_cnt;
|
||||
+ enum dma_transfer_direction dir;
|
||||
+ struct qcom_bam_sgl *bam_sgl;
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
* qcom_bam_sg_init_table - Init QCOM BAM SGL
|
||||
* @bam_sgl: bam sgl
|
||||
* @nents: number of entries in bam sgl
|
||||
--- a/include/linux/dmaengine.h
|
||||
+++ b/include/linux/dmaengine.h
|
||||
@@ -692,6 +692,8 @@ struct dma_filter {
|
||||
* be called after period_len bytes have been transferred.
|
||||
* @device_prep_interleaved_dma: Transfer expression in a generic way.
|
||||
* @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
|
||||
+ * @device_prep_dma_custom_mapping: prepares a dma operation from dma driver
|
||||
+ * specific custom data
|
||||
* @device_config: Pushes a new configuration to a channel, return 0 or an error
|
||||
* code
|
||||
* @device_pause: Pauses any transfer happening on a channel. Returns
|
||||
@@ -783,6 +785,9 @@ struct dma_device {
|
||||
struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
|
||||
struct dma_chan *chan, dma_addr_t dst, u64 data,
|
||||
unsigned long flags);
|
||||
+ struct dma_async_tx_descriptor *(*device_prep_dma_custom_mapping)(
|
||||
+ struct dma_chan *chan, void *data,
|
||||
+ unsigned long flags);
|
||||
|
||||
int (*device_config)(struct dma_chan *chan,
|
||||
struct dma_slave_config *config);
|
||||
@@ -899,6 +904,15 @@ static inline struct dma_async_tx_descri
|
||||
src_sg, src_nents, flags);
|
||||
}
|
||||
|
||||
+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_custom_mapping(
|
||||
+ struct dma_chan *chan,
|
||||
+ void *data,
|
||||
+ unsigned long flags)
|
||||
+{
|
||||
+ return chan->device->device_prep_dma_custom_mapping(chan, data,
|
||||
+ flags);
|
||||
+}
|
||||
+
|
||||
/**
|
||||
* dmaengine_terminate_all() - Terminate all active DMA transfers
|
||||
* @chan: The channel for which to terminate the transfers
|
||||
@ -1,166 +0,0 @@ |
||||
From 02bbf3c46e1e38e9ca699143566903683e3a015d Mon Sep 17 00:00:00 2001
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Thu, 20 Apr 2017 10:45:00 +0530
|
||||
Subject: [PATCH] dts: ipq4019: add nand and qpic bam dma node
|
||||
|
||||
This change adds QPIC BAM dma and NAND driver node's in
|
||||
IPQ4019 device tree, also enable this for AP-DK04.1 based
|
||||
boards.
|
||||
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 75 +++++++++++++++++++++++++++
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 38 ++++++++++++++
|
||||
2 files changed, 113 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
@@ -88,6 +88,86 @@
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ nand_pins: nand_pins {
|
||||
+
|
||||
+ mux_1 {
|
||||
+ pins = "gpio52", "gpio53", "gpio54",
|
||||
+ "gpio55", "gpio56", "gpio61",
|
||||
+ "gpio62", "gpio63", "gpio69";
|
||||
+ function = "qpic_pad";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_2 {
|
||||
+ pins = "gpio67";
|
||||
+ function = "qpic_pad0";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_3 {
|
||||
+ pins = "gpio64";
|
||||
+ function = "qpic_pad1";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_4 {
|
||||
+ pins = "gpio65";
|
||||
+ function = "qpic_pad2";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_5 {
|
||||
+ pins = "gpio66";
|
||||
+ function = "qpic_pad3";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_6 {
|
||||
+ pins = "gpio57";
|
||||
+ function = "qpic_pad4";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_7 {
|
||||
+ pins = "gpio58";
|
||||
+ function = "qpic_pad5";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_8 {
|
||||
+ pins = "gpio59";
|
||||
+ function = "qpic_pad6";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_9 {
|
||||
+ pins = "gpio60";
|
||||
+ function = "qpic_pad7";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_10 {
|
||||
+ pins = "gpio68";
|
||||
+ function = "qpic_pad8";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ pullups {
|
||||
+ pins = "gpio52", "gpio53", "gpio58",
|
||||
+ "gpio59";
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ pulldowns {
|
||||
+ pins = "gpio54", "gpio55", "gpio56",
|
||||
+ "gpio57", "gpio60", "gpio61",
|
||||
+ "gpio62", "gpio63", "gpio64",
|
||||
+ "gpio65", "gpio66", "gpio67",
|
||||
+ "gpio68", "gpio69";
|
||||
+ bias-pull-down;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
@@ -159,5 +239,15 @@
|
||||
watchdog@b017000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ qpic_bam: dma@7984000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ nand: qpic-nand@79b0000 {
|
||||
+ pinctrl-0 = <&nand_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "ok";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -580,5 +580,43 @@
|
||||
"legacy";
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ qpic_bam: dma@7984000 {
|
||||
+ compatible = "qcom,bam-v1.7.0";
|
||||
+ reg = <0x7984000 0x1a000>;
|
||||
+ interrupts = <0 101 0>;
|
||||
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
|
||||
+ clock-names = "bam_clk";
|
||||
+ #dma-cells = <1>;
|
||||
+ qcom,ee = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ nand: qpic-nand@79b0000 {
|
||||
+ compatible = "qcom,ebi2-nandc-bam", "qcom,msm-nand";
|
||||
+ reg = <0x79b0000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ clocks = <&gcc GCC_QPIC_CLK>,
|
||||
+ <&gcc GCC_QPIC_AHB_CLK>;
|
||||
+ clock-names = "core", "aon";
|
||||
+
|
||||
+ dmas = <&qpic_bam 0>,
|
||||
+ <&qpic_bam 1>,
|
||||
+ <&qpic_bam 2>;
|
||||
+ dma-names = "tx", "rx", "cmd";
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ nandcs@0 {
|
||||
+ compatible = "qcom,nandcs";
|
||||
+ reg = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ nand-ecc-strength = <4>;
|
||||
+ nand-ecc-step-size = <512>;
|
||||
+ nand-bus-width = <8>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -1,44 +0,0 @@ |
||||
From patchwork Mon Jul 3 07:47:12 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3,1/2] dts: ipq4019: Fix pinctrl node name
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
X-Patchwork-Id: 9822099
|
||||
Message-Id: <1499068033-24000-2-git-send-email-varada@codeaurora.org>
|
||||
To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
|
||||
mark.rutland@arm.com, linux@armlinux.org.uk,
|
||||
linux-arm-msm@vger.kernel.org,
|
||||
linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
|
||||
Cc: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 3 Jul 2017 13:17:12 +0530
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -40,7 +40,7 @@
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
- pinctrl@0x01000000 {
|
||||
+ pinctrl@1000000 {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -149,7 +149,7 @@
|
||||
reg = <0x1800000 0x60000>;
|
||||
};
|
||||
|
||||
- tlmm: pinctrl@0x01000000 {
|
||||
+ tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq4019-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
gpio-controller;
|
||||
@ -1,78 +0,0 @@ |
||||
From patchwork Mon Jul 3 07:47:13 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3,2/2] dts: ipq4019: Move xo and timer nodes to SoC dtsi
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
X-Patchwork-Id: 9822107
|
||||
Message-Id: <1499068033-24000-3-git-send-email-varada@codeaurora.org>
|
||||
To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
|
||||
mark.rutland@arm.com, linux@armlinux.org.uk,
|
||||
linux-arm-msm@vger.kernel.org,
|
||||
linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
|
||||
Cc: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 3 Jul 2017 13:17:13 +0530
|
||||
|
||||
The node for xo and timer belong to the SoC DTS file.
|
||||
Else, new board DT files may not inherit these nodes.
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 19 -------------------
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 +++++++++++++++
|
||||
2 files changed, 15 insertions(+), 19 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -20,26 +20,7 @@
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
- clocks {
|
||||
- xo: xo {
|
||||
- compatible = "fixed-clock";
|
||||
- clock-frequency = <48000000>;
|
||||
- #clock-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
soc {
|
||||
-
|
||||
-
|
||||
- timer {
|
||||
- compatible = "arm,armv7-timer";
|
||||
- interrupts = <1 2 0xf08>,
|
||||
- <1 3 0xf08>,
|
||||
- <1 4 0xf08>,
|
||||
- <1 1 0xf08>;
|
||||
- clock-frequency = <48000000>;
|
||||
- };
|
||||
-
|
||||
pinctrl@1000000 {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -126,6 +126,21 @@
|
||||
clock-frequency = <32768>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
+
|
||||
+ xo: xo {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <48000000>;
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv7-timer";
|
||||
+ interrupts = <1 2 0xf08>,
|
||||
+ <1 3 0xf08>,
|
||||
+ <1 4 0xf08>,
|
||||
+ <1 1 0xf08>;
|
||||
+ clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
@ -1,11 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
@@ -38,7 +38,7 @@
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
- pinctrl@0x01000000 {
|
||||
+ pinctrl@1000000 {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
@ -1,27 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
@@ -20,24 +20,7 @@
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
- clocks {
|
||||
- xo: xo {
|
||||
- compatible = "fixed-clock";
|
||||
- clock-frequency = <48000000>;
|
||||
- #clock-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
soc {
|
||||
- timer {
|
||||
- compatible = "arm,armv7-timer";
|
||||
- interrupts = <1 2 0xf08>,
|
||||
- <1 3 0xf08>,
|
||||
- <1 4 0xf08>,
|
||||
- <1 1 0xf08>;
|
||||
- clock-frequency = <48000000>;
|
||||
- };
|
||||
-
|
||||
pinctrl@1000000 {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
@ -1,42 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -15,12 +15,39 @@
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
+#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
+ tcsr@194b000 {
|
||||
+ /* select hostmode */
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x194b000 0x100>;
|
||||
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ ess_tcsr@1953000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1953000 0x1000>;
|
||||
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
+ };
|
||||
+
|
||||
+ tcsr@1949000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1949000 0x100>;
|
||||
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
+ };
|
||||
+
|
||||
+ tcsr@1957000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1957000 0x100>;
|
||||
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
+ };
|
||||
+
|
||||
pinctrl@1000000 {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
@ -1,32 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -136,5 +136,29 @@
|
||||
usb2: usb2@60f8800 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ mdio@90000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-switch@c000000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-psgmii@98000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ edma@c080000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ wifi@a000000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ wifi@a800000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -1,17 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -89,14 +89,6 @@
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
cs-gpios = <&tlmm 54 0>;
|
||||
-
|
||||
- mx25l25635e@0 {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
- reg = <0>;
|
||||
- compatible = "mx25l25635e";
|
||||
- spi-max-frequency = <24000000>;
|
||||
- };
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
@ -1,13 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -108,8 +108,8 @@
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
clock-latency-ns = <256000>;
|
||||
};
|
||||
- opp@666000000 {
|
||||
- opp-hz = /bits/ 64 <666000000>;
|
||||
+ opp@716800000 {
|
||||
+ opp-hz = /bits/ 64 <716800000>;
|
||||
clock-latency-ns = <256000>;
|
||||
};
|
||||
};
|
||||
@ -1,115 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
@@ -19,4 +19,112 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
|
||||
|
||||
+ memory {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x80000000 0x10000000>;
|
||||
+ };
|
||||
+
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ apps_bl@87000000 {
|
||||
+ reg = <0x87000000 0x400000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+
|
||||
+ sbl@87400000 {
|
||||
+ reg = <0x87400000 0x100000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+
|
||||
+ cnss_debug@87500000 {
|
||||
+ reg = <0x87500000 0x600000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+
|
||||
+ cpu_context_dump@87b00000 {
|
||||
+ reg = <0x87b00000 0x080000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+
|
||||
+ tz_apps@87b80000 {
|
||||
+ reg = <0x87b80000 0x280000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+
|
||||
+ smem@87e00000 {
|
||||
+ reg = <0x87e00000 0x080000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+
|
||||
+ tz@87e80000 {
|
||||
+ reg = <0x87e80000 0x180000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&spi_0 {
|
||||
+ mx25l25635f@0 {
|
||||
+ compatible = "mx25l25635f", "jedec,spi-nor";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <24000000>;
|
||||
+
|
||||
+ SBL1@0 {
|
||||
+ label = "SBL1";
|
||||
+ reg = <0x0 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ MIBIB@40000 {
|
||||
+ label = "MIBIB";
|
||||
+ reg = <0x40000 0x20000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ QSEE@60000 {
|
||||
+ label = "QSEE";
|
||||
+ reg = <0x60000 0x60000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ CDT@c0000 {
|
||||
+ label = "CDT";
|
||||
+ reg = <0xc0000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ DDRPARAMS@d0000 {
|
||||
+ label = "DDRPARAMS";
|
||||
+ reg = <0xd0000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ APPSBLENV@e0000 {
|
||||
+ label = "APPSBLENV";
|
||||
+ reg = <0xe0000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ APPSBL@f0000 {
|
||||
+ label = "APPSBL";
|
||||
+ reg = <0xf0000 0x80000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ ART@170000 {
|
||||
+ label = "ART";
|
||||
+ reg = <0x170000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ kernel@180000 {
|
||||
+ label = "kernel";
|
||||
+ reg = <0x180000 0x400000>;
|
||||
+ };
|
||||
+ rootfs@580000 {
|
||||
+ label = "rootfs";
|
||||
+ reg = <0x580000 0x1600000>;
|
||||
+ };
|
||||
+ firmware@180000 {
|
||||
+ label = "firmware";
|
||||
+ reg = <0x180000 0x1a00000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
@ -1,10 +0,0 @@ |
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
@@ -18,6 +18,7 @@
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
|
||||
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
Loading…
Reference in new issue