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@ -79,10 +79,10 @@ ar8216_mii_read(struct ar8216_priv *priv, int reg) |
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u16 lo, hi; |
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split_addr((u32) reg, &r1, &r2, &page); |
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phy->bus->write(phy->bus, 0x18, 0, page); |
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mdiobus_write(phy->bus, 0x18, 0, page); |
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msleep(1); /* wait for the page switch to propagate */ |
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lo = phy->bus->read(phy->bus, 0x10 | r2, r1); |
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hi = phy->bus->read(phy->bus, 0x10 | r2, r1 + 1); |
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lo = mdiobus_read(phy->bus, 0x10 | r2, r1); |
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hi = mdiobus_read(phy->bus, 0x10 | r2, r1 + 1); |
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return (hi << 16) | lo; |
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} |
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@ -95,13 +95,13 @@ ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val) |
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u16 lo, hi; |
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split_addr((u32) reg, &r1, &r2, &r3); |
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phy->bus->write(phy->bus, 0x18, 0, r3); |
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mdiobus_write(phy->bus, 0x18, 0, r3); |
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msleep(1); /* wait for the page switch to propagate */ |
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lo = val & 0xffff; |
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hi = (u16) (val >> 16); |
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phy->bus->write(phy->bus, 0x10 | r2, r1 + 1, hi); |
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phy->bus->write(phy->bus, 0x10 | r2, r1, lo); |
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mdiobus_write(phy->bus, 0x10 | r2, r1 + 1, hi); |
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mdiobus_write(phy->bus, 0x10 | r2, r1, lo); |
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} |
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static u32 |
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@ -152,8 +152,8 @@ ar8216_id_chip(struct ar8216_priv *priv) |
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"ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n", |
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(int)(id >> AR8216_CTRL_VERSION_S), |
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(int)(id & AR8216_CTRL_REVISION), |
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priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 2), |
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priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 3)); |
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mdiobus_read(priv->phy->bus, priv->phy->addr, 2), |
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mdiobus_read(priv->phy->bus, priv->phy->addr, 3)); |
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return UNKNOWN; |
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} |
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@ -614,22 +614,22 @@ ar8316_hw_init(struct ar8216_priv *priv) { |
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if ((i == 4) && priv->port4_phy && |
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priv->phy->interface == PHY_INTERFACE_MODE_RGMII) { |
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/* work around for phy4 rgmii mode */ |
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bus->write(bus, i, MII_ATH_DBG_ADDR, 0x12); |
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bus->write(bus, i, MII_ATH_DBG_DATA, 0x480c); |
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mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12); |
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mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c); |
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/* rx delay */ |
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bus->write(bus, i, MII_ATH_DBG_ADDR, 0x0); |
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bus->write(bus, i, MII_ATH_DBG_DATA, 0x824e); |
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mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0); |
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mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e); |
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/* tx delay */ |
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bus->write(bus, i, MII_ATH_DBG_ADDR, 0x5); |
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bus->write(bus, i, MII_ATH_DBG_DATA, 0x3d47); |
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mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5); |
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mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47); |
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msleep(1000); |
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} |
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/* initialize the port itself */ |
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bus->write(bus, i, MII_ADVERTISE, |
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mdiobus_write(bus, i, MII_ADVERTISE, |
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ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
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bus->write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL); |
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bus->write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); |
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mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL); |
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mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); |
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msleep(1000); |
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} |
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