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@ -1,7 +1,7 @@ |
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/*
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/*
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* Ralink SoC specific GPIO support |
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* Ralink SoC specific GPIO support |
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* |
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* |
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> |
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* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* under the terms of the GNU General Public License version 2 as published |
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@ -64,11 +64,13 @@ enum ramips_pio_reg { |
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struct ramips_gpio_chip { |
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struct ramips_gpio_chip { |
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struct gpio_chip chip; |
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struct gpio_chip chip; |
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spinlock_t lock; |
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u8 regs[RAMIPS_GPIO_REG_MAX]; |
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u8 regs[RAMIPS_GPIO_REG_MAX]; |
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}; |
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unsigned long map_base; |
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unsigned long map_size; |
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static void __iomem *ramips_gpio_base; |
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spinlock_t lock; |
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void __iomem *regs_base; |
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}; |
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static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip) |
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static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip) |
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{ |
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{ |
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@ -80,12 +82,12 @@ static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip) |
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static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val) |
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static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val) |
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{ |
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{ |
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__raw_writel(val, ramips_gpio_base + rg->regs[reg]); |
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__raw_writel(val, rg->regs_base + rg->regs[reg]); |
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} |
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} |
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static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg) |
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static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg) |
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{ |
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{ |
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return __raw_readl(ramips_gpio_base + rg->regs[reg]); |
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return __raw_readl(rg->regs_base + rg->regs[reg]); |
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} |
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} |
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static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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@ -164,6 +166,8 @@ static struct ramips_gpio_chip ramips_gpio_chip0 = { |
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[RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET, |
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[RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET, |
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE, |
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE, |
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}, |
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}, |
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.map_base = RALINK_SOC_GPIO_BASE, |
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.map_size = PAGE_SIZE, |
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}; |
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}; |
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static struct ramips_gpio_chip ramips_gpio_chip1 = { |
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static struct ramips_gpio_chip ramips_gpio_chip1 = { |
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@ -188,6 +192,8 @@ static struct ramips_gpio_chip ramips_gpio_chip1 = { |
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[RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET, |
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[RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET, |
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE, |
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE, |
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}, |
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}, |
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.map_base = RALINK_SOC_GPIO_BASE, |
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.map_size = PAGE_SIZE, |
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}; |
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}; |
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static struct ramips_gpio_chip ramips_gpio_chip2 = { |
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static struct ramips_gpio_chip ramips_gpio_chip2 = { |
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@ -212,12 +218,16 @@ static struct ramips_gpio_chip ramips_gpio_chip2 = { |
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[RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET, |
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[RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET, |
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE, |
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE, |
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}, |
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}, |
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.map_base = RALINK_SOC_GPIO_BASE, |
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.map_size = PAGE_SIZE, |
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}; |
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}; |
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static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg) |
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static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg) |
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{ |
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{ |
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spin_lock_init(&rg->lock); |
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spin_lock_init(&rg->lock); |
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rg->regs_base = ioremap(rg->map_base, rg->map_size); |
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/* set polarity to low for all lines */ |
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/* set polarity to low for all lines */ |
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ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0); |
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ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0); |
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@ -226,8 +236,6 @@ static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg) |
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__init int ramips_gpio_init(void) |
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__init int ramips_gpio_init(void) |
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{ |
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{ |
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ramips_gpio_base = ioremap_nocache(RALINK_SOC_GPIO_BASE, PAGE_SIZE); |
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ramips_gpio_chip_add(&ramips_gpio_chip0); |
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ramips_gpio_chip_add(&ramips_gpio_chip0); |
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ramips_gpio_chip_add(&ramips_gpio_chip1); |
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ramips_gpio_chip_add(&ramips_gpio_chip1); |
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ramips_gpio_chip_add(&ramips_gpio_chip2); |
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ramips_gpio_chip_add(&ramips_gpio_chip2); |
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