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03f3002a17
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/* macros for debug output */ |
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#define hcd_dbg(hcd, fmt, args...) \ |
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dev_info(hcd->self.controller, fmt, ## args) |
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#define hcd_err(hcd, fmt, args...) \ |
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dev_err(hcd->self.controller, fmt, ## args) |
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#define hcd_info(hcd, fmt, args...) \ |
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dev_info(hcd->self.controller, fmt, ## args) |
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#define hcd_warn(hcd, fmt, args...) \ |
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dev_warn(hcd->self.controller, fmt, ## args) |
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/*
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#define devdrv_dbg(fmt, args...) \ |
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printk(KERN_INFO "usb_devdrv dbg: ");printk(fmt, ## args) |
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*/ |
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#define devdrv_dbg(fmt, args...) {} |
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#define devdrv_err(fmt, args...) \ |
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printk(KERN_ERR "usb_devdrv error: ");printk(fmt, ## args) |
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#define devdrv_info(fmt, args...) \ |
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printk(KERN_INFO "usb_devdrv: ");printk(fmt, ## args) |
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#define irq_dbg(fmt, args...) \ |
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printk(KERN_INFO "crisv10_irq dbg: ");printk(fmt, ## args) |
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#define irq_err(fmt, args...) \ |
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printk(KERN_ERR "crisv10_irq error: ");printk(fmt, ## args) |
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#define irq_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_irq warn: ");printk(fmt, ## args) |
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#define irq_info(fmt, args...) \ |
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printk(KERN_INFO "crisv10_hcd: ");printk(fmt, ## args) |
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/*
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#define rh_dbg(fmt, args...) \ |
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printk(KERN_DEBUG "crisv10_rh dbg: ");printk(fmt, ## args) |
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*/ |
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#define rh_dbg(fmt, args...) {} |
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#define rh_err(fmt, args...) \ |
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printk(KERN_ERR "crisv10_rh error: ");printk(fmt, ## args) |
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#define rh_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_rh warning: ");printk(fmt, ## args) |
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#define rh_info(fmt, args...) \ |
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printk(KERN_INFO "crisv10_rh: ");printk(fmt, ## args) |
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/*
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#define tc_dbg(fmt, args...) \ |
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printk(KERN_INFO "crisv10_tc dbg: ");printk(fmt, ## args) |
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*/ |
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#define tc_dbg(fmt, args...) {while(0){}} |
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#define tc_err(fmt, args...) \ |
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printk(KERN_ERR "crisv10_tc error: ");printk(fmt, ## args) |
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/*
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#define tc_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_tc warning: ");printk(fmt, ## args) |
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*/ |
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#define tc_warn(fmt, args...) {while(0){}} |
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#define tc_info(fmt, args...) \ |
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printk(KERN_INFO "crisv10_tc: ");printk(fmt, ## args) |
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/* Debug print-outs for various traffic types */ |
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#define intr_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_intr warning: ");printk(fmt, ## args) |
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/*
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#define intr_dbg(fmt, args...) \ |
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printk(KERN_DEBUG "crisv10_intr dbg: ");printk(fmt, ## args) |
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*/ |
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#define intr_dbg(fmt, args...) {while(0){}} |
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#define isoc_err(fmt, args...) \ |
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printk(KERN_ERR "crisv10_isoc error: ");printk(fmt, ## args) |
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/*
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#define isoc_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_isoc warning: ");printk(fmt, ## args) |
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*/ |
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#define isoc_warn(fmt, args...) {while(0){}} |
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/*
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#define isoc_dbg(fmt, args...) \ |
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printk(KERN_INFO "crisv10_isoc dbg: ");printk(fmt, ## args) |
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*/ |
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#define isoc_dbg(fmt, args...) {while(0){}} |
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/*
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#define timer_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_timer warning: ");printk(fmt, ## args) |
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*/ |
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#define timer_warn(fmt, args...) {while(0){}} |
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/*
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#define timer_dbg(fmt, args...) \ |
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printk(KERN_INFO "crisv10_timer dbg: ");printk(fmt, ## args) |
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*/ |
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#define timer_dbg(fmt, args...) {while(0){}} |
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/* Debug printouts for events related to late finishing of URBs */ |
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/*
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#define late_dbg(fmt, args...) \ |
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printk(KERN_INFO "crisv10_late dbg: ");printk(fmt, ## args) |
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*/ |
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#define late_dbg(fmt, args...) {while(0){}} |
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#define late_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_late warning: ");printk(fmt, ## args) |
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/*
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#define errno_dbg(fmt, args...) \ |
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printk(KERN_INFO "crisv10_errno dbg: ");printk(fmt, ## args) |
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*/ |
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#define errno_dbg(fmt, args...) {while(0){}} |
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#define dma_dbg(fmt, args...) \ |
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printk(KERN_INFO "crisv10_dma dbg: ");printk(fmt, ## args) |
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#define dma_err(fmt, args...) \ |
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printk(KERN_ERR "crisv10_dma error: ");printk(fmt, ## args) |
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#define dma_warn(fmt, args...) \ |
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printk(KERN_INFO "crisv10_dma warning: ");printk(fmt, ## args) |
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#define dma_info(fmt, args...) \ |
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printk(KERN_INFO "crisv10_dma: ");printk(fmt, ## args) |
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#define str_dir(pipe) \ |
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(usb_pipeout(pipe) ? "out" : "in") |
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#define str_type(pipe) \ |
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({ \
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char *s = "?"; \
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switch (usb_pipetype(pipe)) { \
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case PIPE_ISOCHRONOUS: s = "iso"; break; \
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case PIPE_INTERRUPT: s = "intr"; break; \
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case PIPE_CONTROL: s = "ctrl"; break; \
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case PIPE_BULK: s = "bulk"; break; \
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}; \
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s; \
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}) |
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