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@ -37,7 +37,7 @@ |
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#define ETH_FCS_LEN 4 |
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#define ETH_FCS_LEN 4 |
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#define AG71XX_DRV_NAME "ag71xx" |
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#define AG71XX_DRV_NAME "ag71xx" |
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#define AG71XX_DRV_VERSION "0.5.7" |
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#define AG71XX_DRV_VERSION "0.5.8" |
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#define AG71XX_NAPI_TX 1 |
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#define AG71XX_NAPI_TX 1 |
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@ -308,13 +308,18 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) |
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static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) |
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static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) |
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{ |
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{ |
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void __iomem *r; |
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switch (reg) { |
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switch (reg) { |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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__raw_writel(value, ag->mac_base + reg); |
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r = ag->mac_base + reg; |
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__raw_writel(value, r); |
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__raw_readl(r); |
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break; |
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break; |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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reg -= AG71XX_REG_MAC_IFCTL; |
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r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL; |
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__raw_writel(value, ag->mac_base2 + reg); |
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__raw_writel(value, r); |
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__raw_readl(r); |
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break; |
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break; |
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default: |
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default: |
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BUG(); |
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BUG(); |
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@ -323,15 +328,17 @@ static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) |
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static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) |
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static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) |
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{ |
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{ |
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void __iomem *r; |
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u32 ret; |
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u32 ret; |
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switch (reg) { |
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switch (reg) { |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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ret = __raw_readl(ag->mac_base + reg); |
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r = ag->mac_base + reg; |
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ret = __raw_readl(r); |
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break; |
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break; |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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reg -= AG71XX_REG_MAC_IFCTL; |
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r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL; |
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ret = __raw_readl(ag->mac_base2 + reg); |
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ret = __raw_readl(r); |
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break; |
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break; |
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default: |
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default: |
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BUG(); |
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BUG(); |
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@ -348,10 +355,12 @@ static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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r = ag->mac_base + reg; |
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r = ag->mac_base + reg; |
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__raw_writel(__raw_readl(r) | mask, r); |
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__raw_writel(__raw_readl(r) | mask, r); |
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__raw_readl(r); |
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break; |
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break; |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL; |
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r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL; |
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__raw_writel(__raw_readl(r) | mask, r); |
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__raw_writel(__raw_readl(r) | mask, r); |
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__raw_readl(r); |
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break; |
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break; |
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default: |
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default: |
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BUG(); |
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BUG(); |
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@ -366,10 +375,12 @@ static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: |
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r = ag->mac_base + reg; |
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r = ag->mac_base + reg; |
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__raw_writel(__raw_readl(r) & ~mask, r); |
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__raw_writel(__raw_readl(r) & ~mask, r); |
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__raw_readl(r); |
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break; |
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break; |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: |
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r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL; |
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r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL; |
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__raw_writel(__raw_readl(r) & ~mask, r); |
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__raw_writel(__raw_readl(r) & ~mask, r); |
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__raw_readl(r); |
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break; |
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break; |
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default: |
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default: |
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BUG(); |
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BUG(); |
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@ -389,6 +400,7 @@ static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) |
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static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) |
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static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) |
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{ |
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{ |
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__raw_writel(value, ag->mii_ctrl); |
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__raw_writel(value, ag->mii_ctrl); |
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__raw_readl(ag->mii_ctrl); |
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} |
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} |
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static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) |
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static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) |
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