Imre Kaloz
16 years ago
parent
b2afb336a2
commit
a0829559f8
@ -1,314 +0,0 @@ |
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--- /dev/null
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+++ b/arch/powerpc/boot/cuboot-magicboxv1.c
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@@ -0,0 +1,41 @@
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+/*
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+ * Old U-boot compatibility for Magicbox v1
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+ *
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+ * Author: Imre Kaloz <kaloz@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include "ops.h"
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+#include "io.h"
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+#include "dcr.h"
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+#include "stdio.h"
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+#include "4xx.h"
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+#include "44x.h"
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+#include "cuboot.h"
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+
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+#define TARGET_4xx
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+#define TARGET_405EP
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+#include "ppcboot.h"
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+
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+static bd_t bd;
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+
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+static void magicboxv1_fixups(void)
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+{
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+ ibm405ep_fixup_clocks(25000000);
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+ ibm4xx_sdram_fixup_memsize();
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+ dt_fixup_mac_addresses(&bd.bi_enetaddr);
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+}
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+
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+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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+ unsigned long r6, unsigned long r7)
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+{
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+ CUBOOT_INIT();
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+ platform_ops.fixups = magicboxv1_fixups;
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+ platform_ops.exit = ibm40x_dbcr_reset;
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+ fdt_init(_dtb_start);
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+ serial_console_init();
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+}
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+
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--- /dev/null
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+++ b/arch/powerpc/boot/dts/magicboxv1.dts
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@@ -0,0 +1,217 @@
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+/*
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+ * Device Tree Source for Magicbox v1
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+ *
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+ * Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
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+ *
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+ * Based on walnut.dts
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without
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+ * any warranty of any kind, whether express or implied.
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+ */
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+
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+/dts-v1/;
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ model = "magicboxv1";
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+ compatible = "magicboxv1";
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+ dcr-parent = <&{/cpus/cpu@0}>;
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+
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+ aliases {
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+ ethernet0 = &EMAC;
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+ serial0 = &UART;
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ model = "PowerPC,405EP";
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+ reg = <0x00000000>;
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+ clock-frequency = <0xbebc200>; /* Filled in by zImage */
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+ timebase-frequency = <0>; /* Filled in by zImage */
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+ i-cache-line-size = <20>;
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+ d-cache-line-size = <20>;
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+ i-cache-size = <4000>;
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+ d-cache-size = <4000>;
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+ dcr-controller;
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+ dcr-access-method = "native";
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+ };
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x00000000 0x00000000>; /* Filled in by zImage */
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+ };
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+
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+ UIC0: interrupt-controller {
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+ compatible = "ibm,uic";
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+ interrupt-controller;
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+ cell-index = <0>;
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+ dcr-reg = <0x0c0 0x009>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ plb {
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+ compatible = "ibm,plb3";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ SDRAM0: memory-controller {
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+ compatible = "ibm,sdram-405ep";
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+ dcr-reg = <0x010 0x002>;
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+ };
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+
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+ MAL: mcmal {
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+ compatible = "ibm,mcmal-405ep", "ibm,mcmal";
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+ dcr-reg = <0x180 0x062>;
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+ num-tx-chans = <4>;
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+ num-rx-chans = <2>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <
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+ 0xb 0x4 /* TXEOB */
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+ 0xc 0x4 /* RXEOB */
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+ 0xa 0x4 /* SERR */
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+ 0xd 0x4 /* TXDE */
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+ 0xe 0x4 /* RXDE */>;
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+ };
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+
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+ POB0: opb {
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+ compatible = "ibm,opb-405ep", "ibm,opb";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0xef600000 0xef600000 0x00a00000>;
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+ dcr-reg = <0x0a0 0x005>;
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ UART: serial@ef600300 {
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+ device_type = "serial";
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+ compatible = "ns16550";
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+ reg = <0xef600300 0x00000008>;
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+ virtual-reg = <0xef600300>;
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+ clock-frequency = <0>; /* Filled in by zImage */
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+ current-speed = <115200>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x0 0x4>;
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+ };
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+
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+ IIC: i2c@ef600500 {
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+ compatible = "ibm,iic-405ep", "ibm,iic";
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+ reg = <0xef600500 0x00000011>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x2 0x4>;
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+ };
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+
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+ GPIO: gpio@ef600700 {
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+ compatible = "ibm,gpio-405ep";
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+ reg = <0xef600700 0x00000020>;
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+ };
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+
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+ EMAC: ethernet@ef600800 {
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+ linux,network-index = <0x0>;
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+ device_type = "network";
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+ compatible = "ibm,emac-405ep", "ibm,emac";
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <
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+ 0xf 0x4 /* Ethernet */
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+ 0x9 0x4 /* Ethernet Wake Up */>;
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+ local-mac-address = [000000000000]; /* Filled in by zImage */
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+ reg = <0xef600800 0x00000070>;
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+ mal-device = <&MAL>;
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+ mal-tx-channel = <0>;
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+ mal-rx-channel = <0>;
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+ cell-index = <0>;
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+ max-frame-size = <0x5dc>;
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+ rx-fifo-size = <0x1000>;
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+ tx-fifo-size = <0x800>;
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+ phy-mode = "mii";
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+ phy-map = <0x00000000>;
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+ };
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+
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+ };
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+
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+ EBC0: ebc {
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+ compatible = "ibm,ebc-405ep", "ibm,ebc";
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+ dcr-reg = <0x012 0x002>;
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ /* The ranges property is supplied by the bootwrapper
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+ * and is based on the firmware's configuration of the
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+ * EBC bridge
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+ */
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ nor_flash@ffc00000 {
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+ compatible = "cfi-flash";
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+ bank-width = <2>;
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+ reg = <0x00000000 0xffc00000 0x00400000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ partition@0 {
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+ label = "linux";
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+ reg = <0x0 0x120000>;
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+ };
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+ partition@120000 {
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+ label = "rootfs";
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+ reg = <0x120000 0x2a0000>;
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+ };
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+ partition@3c0000 {
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+ label = "u-boot";
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+ reg = <0x3c0000 0x30000>;
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+ read-only;
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+ };
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+ };
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+ };
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+
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+ PCI0: pci@ec000000 {
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+ device_type = "pci";
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ #address-cells = <3>;
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+ compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
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+ primary;
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+ reg = <0xeec00000 0x00000008 /* Config space access */
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+ 0xeed80000 0x00000004 /* IACK */
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+ 0xeed80000 0x00000004 /* Special cycle */
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+ 0xef480000 0x00000040>; /* Internal registers */
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+
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+ /* Outbound ranges, one memory and one IO,
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+ * later cannot be changed. Chip supports a second
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+ * IO range but we don't use it for now
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+ */
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+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
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+ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
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+
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+ /* Inbound 2GB range starting at 0 */
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+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
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+
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+ /* Magicbox v1 has all 4 IRQ pins tied together per slot */
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+ interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
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+ interrupt-map = <
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+ /* IDSEL 1 */
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+ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
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+
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+ /* IDSEL 2 */
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+ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
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+
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+ /* IDSEL 3 */
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+ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
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+
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+ /* IDSEL 4 */
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+ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
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+ >;
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+ };
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+ };
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+
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+ chosen {
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+ linux,stdout-path = "/plb/opb/serial@ef600300";
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+ };
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+};
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--- a/arch/powerpc/boot/Makefile
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+++ b/arch/powerpc/boot/Makefile
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@@ -75,7 +75,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
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cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
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cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
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virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
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- cuboot-acadia.c cuboot-amigaone.c
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+ cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c
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src-boot := $(src-wlib) $(src-plat) empty.c
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src-boot := $(addprefix $(obj)/, $(src-boot))
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@@ -192,6 +192,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImag
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image-$(CONFIG_EP405) += dtbImage.ep405
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image-$(CONFIG_WALNUT) += treeImage.walnut
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image-$(CONFIG_ACADIA) += cuImage.acadia
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+image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
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# Board ports in arch/powerpc/platform/44x/Kconfig
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image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
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--- a/arch/powerpc/platforms/40x/Kconfig
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+++ b/arch/powerpc/platforms/40x/Kconfig
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@@ -49,6 +49,16 @@ config KILAUEA
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help
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This option enables support for the AMCC PPC405EX evaluation board.
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+config MAGICBOXV1
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+ bool "Magicbox v1"
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+ depends on 40x
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+ default n
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+ select PPC40x_SIMPLE
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+ select 405EP
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+ select PCI
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+ help
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+ This option enables support for the Magicbox v1 board.
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+
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config MAKALU
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bool "Makalu"
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depends on 40x
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--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
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+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
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@@ -51,7 +51,8 @@ machine_device_initcall(ppc40x_simple, p
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* board.c file for it rather than adding it to this list.
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*/
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static char *board[] __initdata = {
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- "amcc,acadia"
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+ "amcc,acadia",
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+ "magicboxv1",
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};
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static int __init ppc40x_probe(void)
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@ -1,375 +0,0 @@ |
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--- a/arch/powerpc/boot/Makefile
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+++ b/arch/powerpc/boot/Makefile
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@@ -76,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
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cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
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virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
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cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c \
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- cuboot-magicboxv2.c
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+ cuboot-magicboxv2.c cuboot-openrb-light.c
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src-boot := $(src-wlib) $(src-plat) empty.c
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src-boot := $(addprefix $(obj)/, $(src-boot))
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@@ -195,6 +195,7 @@ image-$(CONFIG_WALNUT) += treeImage.wa
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image-$(CONFIG_ACADIA) += cuImage.acadia
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image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
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image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
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+image-$(CONFIG_OPENRB_LIGHT) += cuImage.openrb-light
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# Board ports in arch/powerpc/platform/44x/Kconfig
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image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
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--- a/arch/powerpc/platforms/40x/Kconfig
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+++ b/arch/powerpc/platforms/40x/Kconfig
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@@ -79,6 +79,16 @@ config MAKALU
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help
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This option enables support for the AMCC PPC405EX board.
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+config OPENRB_LIGHT
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+ bool "OpenRB Light"
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+ depends on 40x
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+ default n
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+ select PPC40x_SIMPLE
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+ select 405EP
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+ select PCI
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+ help
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+ This option enables support for the OpenRB Light board.
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+
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#config REDWOOD_5
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# bool "Redwood-5"
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# depends on 40x
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--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
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+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
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@@ -54,6 +54,7 @@ static char *board[] __initdata = {
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"amcc,acadia",
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"magicboxv1",
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"magicboxv2",
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+ "openrb,light",
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};
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static int __init ppc40x_probe(void)
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--- /dev/null
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+++ b/arch/powerpc/boot/cuboot-openrb-light.c
|
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@@ -0,0 +1,69 @@
|
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+/*
|
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+ * Old U-boot compatibility for OpenRB Light board
|
||||
+ *
|
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+ * Author: Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
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+
|
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+#include "ops.h"
|
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+#include "io.h"
|
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+#include "dcr.h"
|
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+#include "stdio.h"
|
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+#include "4xx.h"
|
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+#include "44x.h"
|
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+#include "cuboot.h"
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+
|
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+#define TARGET_4xx
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+#define TARGET_405EP
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+#include "ppcboot.h"
|
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+
|
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+static bd_t bd;
|
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+
|
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+static void fixup_cf_card(void)
|
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+{
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+#define DCRN_CPC0_PCI_BASE 0xf9
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+#define CF_CS0_BASE 0xff100000
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+#define CF_CS1_BASE 0xff200000
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+
|
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+ /* Turn on PerWE instead of PCIsomething */
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+ mtdcr(DCRN_CPC0_PCI_BASE,
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+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
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+
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+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
|
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
|
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
|
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+
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+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
|
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
|
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
|
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
|
||||
+
|
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+#undef DCRN_CPC0_PCI_BASE
|
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+#undef CF_CS0_BASE
|
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+#undef CF_CS1_BASE
|
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+}
|
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+
|
||||
+static void openrb_light_fixups(void)
|
||||
+{
|
||||
+ fixup_cf_card();
|
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+ ibm405ep_fixup_clocks(33333000);
|
||||
+ ibm4xx_sdram_fixup_memsize();
|
||||
+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
||||
+}
|
||||
+
|
||||
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
+ unsigned long r6, unsigned long r7)
|
||||
+{
|
||||
+ CUBOOT_INIT();
|
||||
+ platform_ops.fixups = openrb_light_fixups;
|
||||
+ platform_ops.exit = ibm40x_dbcr_reset;
|
||||
+ fdt_init(_dtb_start);
|
||||
+ serial_console_init();
|
||||
+}
|
||||
+
|
||||
--- /dev/null
|
||||
+++ b/arch/powerpc/boot/dts/openrb-light.dts
|
||||
@@ -0,0 +1,252 @@
|
||||
+/*
|
||||
+ * Device Tree Source for OpenRB Light board
|
||||
+ *
|
||||
+ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * Based on magicboxv2.dts
|
||||
+ *
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without
|
||||
+ * any warranty of any kind, whether express or implied.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ model = "openrb,light";
|
||||
+ compatible = "openrb,light";
|
||||
+ dcr-parent = <&{/cpus/cpu@0}>;
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &EMAC0;
|
||||
+ serial0 = &UART0;
|
||||
+ serial1 = &UART1;
|
||||
+ };
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ cpu@0 {
|
||||
+ device_type = "cpu";
|
||||
+ model = "PowerPC,405EP";
|
||||
+ reg = <0x00000000>;
|
||||
+ clock-frequency = <0xbebc200>; /* Filled in by zImage */
|
||||
+ timebase-frequency = <0>; /* Filled in by zImage */
|
||||
+ i-cache-line-size = <20>;
|
||||
+ d-cache-line-size = <20>;
|
||||
+ i-cache-size = <4000>;
|
||||
+ d-cache-size = <4000>;
|
||||
+ dcr-controller;
|
||||
+ dcr-access-method = "native";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ memory {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
+ };
|
||||
+
|
||||
+ UIC0: interrupt-controller {
|
||||
+ compatible = "ibm,uic";
|
||||
+ interrupt-controller;
|
||||
+ cell-index = <0>;
|
||||
+ dcr-reg = <0x0c0 0x009>;
|
||||
+ #address-cells = <0>;
|
||||
+ #size-cells = <0>;
|
||||
+ #interrupt-cells = <2>;
|
||||
+ };
|
||||
+
|
||||
+ plb {
|
||||
+ compatible = "ibm,plb3";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+ clock-frequency = <0>; /* Filled in by zImage */
|
||||
+
|
||||
+ SDRAM0: memory-controller {
|
||||
+ compatible = "ibm,sdram-405ep";
|
||||
+ dcr-reg = <0x010 0x002>;
|
||||
+ };
|
||||
+
|
||||
+ MAL: mcmal {
|
||||
+ compatible = "ibm,mcmal-405ep", "ibm,mcmal";
|
||||
+ dcr-reg = <0x180 0x062>;
|
||||
+ num-tx-chans = <4>;
|
||||
+ num-rx-chans = <2>;
|
||||
+ interrupt-parent = <&UIC0>;
|
||||
+ interrupts = <
|
||||
+ 0xb 0x4 /* TXEOB */
|
||||
+ 0xc 0x4 /* RXEOB */
|
||||
+ 0xa 0x4 /* SERR */
|
||||
+ 0xd 0x4 /* TXDE */
|
||||
+ 0xe 0x4 /* RXDE */>;
|
||||
+ };
|
||||
+
|
||||
+ OPB0: opb {
|
||||
+ compatible = "ibm,opb-405ep", "ibm,opb";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0xef600000 0xef600000 0x00a00000>;
|
||||
+ dcr-reg = <0x0a0 0x005>;
|
||||
+ clock-frequency = <0>; /* Filled in by zImage */
|
||||
+
|
||||
+ UART0: serial@ef600300 {
|
||||
+ device_type = "serial";
|
||||
+ compatible = "ns16550";
|
||||
+ reg = <0xef600300 0x00000008>;
|
||||
+ virtual-reg = <0xef600300>;
|
||||
+ clock-frequency = <0>; /* Filled in by zImage */
|
||||
+ current-speed = <115200>;
|
||||
+ interrupt-parent = <&UIC0>;
|
||||
+ interrupts = <0x0 0x4>;
|
||||
+ };
|
||||
+
|
||||
+ UART1: serial@ef600400 {
|
||||
+ device_type = "serial";
|
||||
+ compatible = "ns16550";
|
||||
+ reg = <0xef600400 0x00000008>;
|
||||
+ virtual-reg = <0xef600400>;
|
||||
+ clock-frequency = <0>; /* Filled in by zImage */
|
||||
+ current-speed = <115200>;
|
||||
+ interrupt-parent = <&UIC0>;
|
||||
+ interrupts = <0x1 0x4>;
|
||||
+ };
|
||||
+
|
||||
+ IIC: i2c@ef600500 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "ibm,iic-405ep", "ibm,iic";
|
||||
+ reg = <0xef600500 0x00000011>;
|
||||
+ interrupt-parent = <&UIC0>;
|
||||
+ interrupts = <0x2 0x4>;
|
||||
+
|
||||
+ eeprom@50 {
|
||||
+ compatible = "at24,24c16";
|
||||
+ reg = <0x50>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ GPIO0: gpio-controller@ef600700 {
|
||||
+ compatible = "ibm,ppc4xx-gpio";
|
||||
+ reg = <0xef600700 0x00000020>;
|
||||
+ #gpio-cells = <2>;
|
||||
+ gpio-controller;
|
||||
+ };
|
||||
+
|
||||
+ EMAC0: ethernet@ef600800 {
|
||||
+ linux,network-index = <0x0>;
|
||||
+ device_type = "network";
|
||||
+ compatible = "ibm,emac-405ep", "ibm,emac";
|
||||
+ interrupt-parent = <&UIC0>;
|
||||
+ interrupts = <
|
||||
+ 0xf 0x4 /* Ethernet */
|
||||
+ 0x9 0x4 /* Ethernet Wake Up */>;
|
||||
+ local-mac-address = [000000000000]; /* Filled in by zImage */
|
||||
+ reg = <0xef600800 0x00000070>;
|
||||
+ mal-device = <&MAL>;
|
||||
+ mal-tx-channel = <0>;
|
||||
+ mal-rx-channel = <0>;
|
||||
+ cell-index = <0>;
|
||||
+ max-frame-size = <0x5dc>;
|
||||
+ rx-fifo-size = <0x1000>;
|
||||
+ tx-fifo-size = <0x800>;
|
||||
+ phy-mode = "mii";
|
||||
+ phy-map = <0x00000000>;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ user {
|
||||
+ label = "openrb:green:user";
|
||||
+ gpios = <&GPIO0 2 1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ EBC0: ebc {
|
||||
+ compatible = "ibm,ebc-405ep", "ibm,ebc";
|
||||
+ dcr-reg = <0x012 0x002>;
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <1>;
|
||||
+ /* The ranges property is supplied by the bootwrapper
|
||||
+ * and is based on the firmware's configuration of the
|
||||
+ * EBC bridge
|
||||
+ */
|
||||
+ clock-frequency = <0>; /* Filled in by zImage */
|
||||
+
|
||||
+ cf_card@ff100000 {
|
||||
+ compatible = "magicbox-cf", "pata-magicbox-cf";
|
||||
+ reg = <0x00000000 0xff100000 0x00001000
|
||||
+ 0x00000000 0xff200000 0x00001000>;
|
||||
+ interrupt-parent = <&UIC0>;
|
||||
+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
|
||||
+ };
|
||||
+
|
||||
+ nor_flash@ff800000 {
|
||||
+ compatible = "cfi-flash";
|
||||
+ bank-width = <2>;
|
||||
+ reg = <0x00000000 0xff800000 0x00800000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ partition@0 {
|
||||
+ label = "linux";
|
||||
+ reg = <0x0 0x120000>;
|
||||
+ };
|
||||
+ partition@120000 {
|
||||
+ label = "rootfs";
|
||||
+ reg = <0x120000 0x6a0000>;
|
||||
+ };
|
||||
+ partition@7c0000 {
|
||||
+ label = "u-boot";
|
||||
+ reg = <0x7c0000 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ PCI0: pci@ec000000 {
|
||||
+ device_type = "pci";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ #size-cells = <2>;
|
||||
+ #address-cells = <3>;
|
||||
+ compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
|
||||
+ primary;
|
||||
+ reg = <0xeec00000 0x00000008 /* Config space access */
|
||||
+ 0xeed80000 0x00000004 /* IACK */
|
||||
+ 0xeed80000 0x00000004 /* Special cycle */
|
||||
+ 0xef480000 0x00000040>; /* Internal registers */
|
||||
+
|
||||
+ /* Outbound ranges, one memory and one IO,
|
||||
+ * later cannot be changed. Chip supports a second
|
||||
+ * IO range but we don't use it for now
|
||||
+ */
|
||||
+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
|
||||
+ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
+
|
||||
+ /* Inbound 2GB range starting at 0 */
|
||||
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
+
|
||||
+ interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
+ interrupt-map = <
|
||||
+ /* IDSEL 1 */
|
||||
+ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
|
||||
+
|
||||
+ /* IDSEL 2 */
|
||||
+ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
|
||||
+
|
||||
+ /* IDSEL 3 */
|
||||
+ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
|
||||
+
|
||||
+ /* IDSEL 4 */
|
||||
+ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
|
||||
+ >;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
+ };
|
||||
+};
|
||||
Loading…
Reference in new issue