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@ -90,7 +90,6 @@ static struct irqaction ar71xx_gpio_irqaction = { |
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.name = "cascade [AR71XX GPIO]", |
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.name = "cascade [AR71XX GPIO]", |
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}; |
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}; |
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#define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) |
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#define GPIO_INT_ALL 0xffff |
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#define GPIO_INT_ALL 0xffff |
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static void __init ar71xx_gpio_irq_init(void) |
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static void __init ar71xx_gpio_irq_init(void) |
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@ -108,11 +107,9 @@ static void __init ar71xx_gpio_irq_init(void) |
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__raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); |
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__raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); |
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for (i = AR71XX_GPIO_IRQ_BASE; |
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for (i = AR71XX_GPIO_IRQ_BASE; |
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i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) { |
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i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) |
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irq_desc[i].status = GPIO_IRQ_INIT_STATUS; |
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set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip, |
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set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip, |
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handle_level_irq); |
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handle_level_irq); |
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} |
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setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); |
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setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); |
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} |
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} |
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@ -245,11 +242,9 @@ static void __init ar71xx_misc_irq_init(void) |
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} |
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} |
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for (i = AR71XX_MISC_IRQ_BASE; |
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for (i = AR71XX_MISC_IRQ_BASE; |
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) { |
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) |
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irq_desc[i].status = IRQ_DISABLED; |
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set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip, |
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set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip, |
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handle_level_irq); |
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handle_level_irq); |
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} |
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setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); |
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setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); |
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} |
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} |
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