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ipq806x: reduce PCIe buffer size setting to fix potential data corruption issues

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Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47545
master
Felix Fietkau 9 years ago
parent 49d4a980d7
commit 9c114740ef
2 changed files with 4 additions and 4 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch
  2. 4
      target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch

4
target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch
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@ -229,8 +229,8 @@
+ writel(upper_32_bits(pp->mem_bus_addr), + writel(upper_32_bits(pp->mem_bus_addr),
+ pcie->dbi + PCIE20_PLR_IATU_UTAR); + pcie->dbi + PCIE20_PLR_IATU_UTAR);
+ +
+ /* 1K PCIE buffer setting */ + /* 256B PCIE buffer setting */
+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
+ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
+} +}
+ +

4
target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch
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@ -229,8 +229,8 @@
+ writel(upper_32_bits(pp->mem_bus_addr), + writel(upper_32_bits(pp->mem_bus_addr),
+ pcie->dbi + PCIE20_PLR_IATU_UTAR); + pcie->dbi + PCIE20_PLR_IATU_UTAR);
+ +
+ /* 1K PCIE buffer setting */ + /* 256B PCIE buffer setting */
+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
+ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
+} +}
+ +

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