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@ -51,6 +51,24 @@ ramips_fe_rr(unsigned reg) |
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return __raw_readl(ramips_fe_base + reg); |
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} |
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static inline void |
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ramips_fe_int_disable(u32 mask) |
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{ |
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ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) & ~mask, |
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RAMIPS_FE_INT_ENABLE); |
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/* flush write */ |
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ramips_fe_rr(RAMIPS_FE_INT_ENABLE); |
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} |
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static inline void |
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ramips_fe_int_enable(u32 mask) |
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{ |
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ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | mask, |
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RAMIPS_FE_INT_ENABLE); |
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/* flush write */ |
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ramips_fe_rr(RAMIPS_FE_INT_ENABLE); |
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} |
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static void |
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ramips_cleanup_dma(struct raeth_priv *re) |
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{ |
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@ -229,8 +247,7 @@ ramips_eth_rx_hw(unsigned long ptr) |
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if (max_rx == 0) |
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tasklet_schedule(&priv->rx_tasklet); |
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else |
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ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | RAMIPS_RX_DLY_INT, |
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RAMIPS_FE_INT_ENABLE); |
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ramips_fe_int_enable(RAMIPS_RX_DLY_INT); |
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} |
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static void |
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@ -248,8 +265,7 @@ ramips_eth_tx_housekeeping(unsigned long ptr) |
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priv->skb_free_idx = 0; |
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} |
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ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | RAMIPS_TX_DLY_INT, |
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RAMIPS_FE_INT_ENABLE); |
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ramips_fe_int_enable(RAMIPS_TX_DLY_INT); |
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} |
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static int |
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@ -284,8 +300,7 @@ ramips_eth_irq(int irq, void *dev) |
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ramips_fe_wr(0xFFFFFFFF, RAMIPS_FE_INT_STATUS); |
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if (fe_int & RAMIPS_RX_DLY_INT) { |
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ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) & ~(RAMIPS_RX_DLY_INT), |
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RAMIPS_FE_INT_ENABLE); |
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ramips_fe_int_disable(RAMIPS_RX_DLY_INT); |
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tasklet_schedule(&priv->rx_tasklet); |
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} |
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