adds a few ethernet fixes Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 49132
parent
8b8dfeb027
commit
8bda1ae2cc
@ -1,314 +0,0 @@ |
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From e301da64a9fd2ebc24d4c9b2d184681ec833fd72 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 23 Mar 2016 18:31:48 +0100
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Subject: [PATCH 73/78] net-next: mediatek: add support for IRQ grouping
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The ethernet core has 3 IRQs. using the IRQ grouping registers we are able
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to separate TX and RX IRQs, which allows us to service them on separate
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cores. This patch splits the irq handler into 2 separate functiosn, one for
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TX and another for RX. The TX housekeeping is split out of the NAPI handler.
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Instead we use a tasklet to handle housekeeping.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 +++++++++++++++++----------
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++-
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2 files changed, 86 insertions(+), 41 deletions(-)
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diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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index bbcd607..2097ae1 100644
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -757,7 +757,7 @@ drop:
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}
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static int mtk_poll_rx(struct napi_struct *napi, int budget,
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- struct mtk_eth *eth, u32 rx_intr)
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+ struct mtk_eth *eth)
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{
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struct mtk_rx_ring *ring = ð->rx_ring;
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int idx = ring->calc_idx;
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@@ -843,12 +843,12 @@ release_desc:
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}
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if (done < budget)
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- mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
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+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
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return done;
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}
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-static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
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+static int mtk_poll_tx(struct mtk_eth *eth, int budget)
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{
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struct mtk_tx_ring *ring = ð->tx_ring;
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struct mtk_tx_dma *desc;
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@@ -911,9 +911,7 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
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}
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/* read hw index again make sure no new tx packet */
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- if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
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- *tx_again = true;
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- else
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+ if (cpu == dma && cpu == mtk_r32(eth, MTK_QTX_DRX_PTR))
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mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
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if (!total)
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@@ -925,27 +923,27 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
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return total;
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}
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+static void mtk_clean_tx_tasklet(unsigned long arg)
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+{
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+ struct mtk_eth *eth = (struct mtk_eth *)arg;
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+
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+ if (mtk_poll_tx(eth, MTK_NAPI_WEIGHT) > 0)
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+ tasklet_schedule(ð->tx_clean_tasklet);
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+ else
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+ mtk_irq_enable(eth, MTK_TX_DONE_INT);
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+}
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+
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static int mtk_poll(struct napi_struct *napi, int budget)
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{
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struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
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- u32 status, status2, mask, tx_intr, rx_intr, status_intr;
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- int tx_done, rx_done;
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- bool tx_again = false;
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+ u32 status, status2, mask, status_intr;
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+ int rx_done = 0;
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status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
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status2 = mtk_r32(eth, MTK_INT_STATUS2);
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- tx_intr = MTK_TX_DONE_INT;
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- rx_intr = MTK_RX_DONE_INT;
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status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
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- tx_done = 0;
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- rx_done = 0;
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- tx_again = 0;
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- if (status & tx_intr)
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- tx_done = mtk_poll_tx(eth, budget, &tx_again);
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-
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- if (status & rx_intr)
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- rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
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+ rx_done = mtk_poll_rx(napi, budget, eth);
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if (unlikely(status2 & status_intr)) {
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mtk_stats_update(eth);
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@@ -954,20 +952,20 @@ static int mtk_poll(struct napi_struct *napi, int budget)
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if (unlikely(netif_msg_intr(eth))) {
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mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
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- netdev_info(eth->netdev[0],
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- "done tx %d, rx %d, intr 0x%08x/0x%x\n",
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- tx_done, rx_done, status, mask);
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+ dev_info(eth->dev,
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+ "done rx %d, intr 0x%08x/0x%x\n",
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+ rx_done, status, mask);
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}
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- if (tx_again || rx_done == budget)
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+ if (rx_done == budget)
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return budget;
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status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
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- if (status & (tx_intr | rx_intr))
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+ if (status & MTK_RX_DONE_INT)
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return budget;
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napi_complete(napi);
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- mtk_irq_enable(eth, tx_intr | rx_intr);
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+ mtk_irq_enable(eth, MTK_RX_DONE_INT);
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return rx_done;
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}
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@@ -1196,22 +1194,43 @@ static void mtk_tx_timeout(struct net_device *dev)
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schedule_work(ð->pending_work);
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}
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-static irqreturn_t mtk_handle_irq(int irq, void *_eth)
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+static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
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{
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struct mtk_eth *eth = _eth;
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u32 status;
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status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
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+ status &= ~MTK_TX_DONE_INT;
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+
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if (unlikely(!status))
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return IRQ_NONE;
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- if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
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+ if (status & MTK_RX_DONE_INT) {
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if (likely(napi_schedule_prep(ð->rx_napi)))
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__napi_schedule(ð->rx_napi);
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- } else {
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- mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
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+ mtk_irq_disable(eth, MTK_RX_DONE_INT);
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}
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- mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
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+ mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
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+{
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+ struct mtk_eth *eth = _eth;
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+ u32 status;
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+
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+ status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
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+ status &= ~MTK_RX_DONE_INT;
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+
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+ if (unlikely(!status))
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+ return IRQ_NONE;
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+
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+ if (status & MTK_TX_DONE_INT) {
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+ tasklet_schedule(ð->tx_clean_tasklet);
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+ mtk_irq_disable(eth, MTK_TX_DONE_INT);
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+ }
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+ mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
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return IRQ_HANDLED;
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}
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@@ -1224,7 +1243,7 @@ static void mtk_poll_controller(struct net_device *dev)
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u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
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mtk_irq_disable(eth, int_mask);
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- mtk_handle_irq(dev->irq, dev);
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+ mtk_handle_irq(dev->irq[0], dev);
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mtk_irq_enable(eth, int_mask);
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}
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#endif
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@@ -1345,7 +1364,11 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
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/* Enable RX VLan Offloading */
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mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
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- err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
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+ err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
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+ dev_name(eth->dev), eth);
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+ if (err)
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+ return err;
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+ err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
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dev_name(eth->dev), eth);
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if (err)
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return err;
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@@ -1361,7 +1384,11 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
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mtk_w32(eth, 0, MTK_RST_GL);
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/* FE int grouping */
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- mtk_w32(eth, 0, MTK_FE_INT_GRP);
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+ mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
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+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
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+ mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
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+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
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+ mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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for (i = 0; i < 2; i++) {
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u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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@@ -1409,7 +1436,9 @@ static void mtk_uninit(struct net_device *dev)
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phy_disconnect(mac->phy_dev);
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mtk_mdio_cleanup(eth);
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mtk_irq_disable(eth, ~0);
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- free_irq(dev->irq, dev);
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+ free_irq(eth->irq[0], dev);
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+ free_irq(eth->irq[1], dev);
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+ free_irq(eth->irq[2], dev);
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}
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static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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@@ -1684,10 +1713,10 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
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dev_err(eth->dev, "error bringing up device\n");
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goto free_netdev;
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}
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- eth->netdev[id]->irq = eth->irq;
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+ eth->netdev[id]->irq = eth->irq[0];
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netif_info(eth, probe, eth->netdev[id],
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"mediatek frame engine at 0x%08lx, irq %d\n",
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- eth->netdev[id]->base_addr, eth->netdev[id]->irq);
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+ eth->netdev[id]->base_addr, eth->irq[0]);
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return 0;
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@@ -1704,6 +1733,7 @@ static int mtk_probe(struct platform_device *pdev)
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struct mtk_soc_data *soc;
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struct mtk_eth *eth;
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int err;
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+ int i;
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match = of_match_device(of_mtk_match, &pdev->dev);
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soc = (struct mtk_soc_data *)match->data;
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@@ -1738,10 +1768,12 @@ static int mtk_probe(struct platform_device *pdev)
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return PTR_ERR(eth->rstc);
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}
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- eth->irq = platform_get_irq(pdev, 0);
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- if (eth->irq < 0) {
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- dev_err(&pdev->dev, "no IRQ resource found\n");
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- return -ENXIO;
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+ for (i = 0; i < 3; i++) {
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+ eth->irq[i] = platform_get_irq(pdev, i);
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+ if (eth->irq[i] < 0) {
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+ dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
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+ return -ENXIO;
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+ }
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}
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eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
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@@ -1785,6 +1817,9 @@ static int mtk_probe(struct platform_device *pdev)
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netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_poll,
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MTK_NAPI_WEIGHT);
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+ tasklet_init(ð->tx_clean_tasklet,
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+ mtk_clean_tx_tasklet, (unsigned long)eth);
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+
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platform_set_drvdata(pdev, eth);
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return 0;
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diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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index eed626d..4cfb40c 100644
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -68,6 +68,10 @@
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/* Unicast Filter MAC Address Register - High */
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#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
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+/* PDMA Interrupt grouping registers */
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+#define MTK_PDMA_INT_GRP1 0xa50
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+#define MTK_PDMA_INT_GRP2 0xa54
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+
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/* QDMA TX Queue Configuration Registers */
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#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
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#define QDMA_RES_THRES 4
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@@ -124,6 +128,11 @@
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#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
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MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
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+/* QDMA Interrupt grouping registers */
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+#define MTK_QDMA_INT_GRP1 0x1a20
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+#define MTK_QDMA_INT_GRP2 0x1a24
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+#define MTK_RLS_DONE_INT BIT(0)
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+
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/* QDMA Interrupt Status Register */
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#define MTK_QDMA_INT_MASK 0x1A1C
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@@ -374,7 +383,7 @@ struct mtk_eth {
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struct net_device dummy_dev;
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struct net_device *netdev[MTK_MAX_DEVS];
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struct mtk_mac *mac[MTK_MAX_DEVS];
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- int irq;
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+ int irq[3];
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u32 msg_enable;
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unsigned long sysclk;
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struct regmap *ethsys;
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@@ -391,6 +400,7 @@ struct mtk_eth {
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struct clk *clk_gp2;
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struct mii_bus *mii_bus;
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struct work_struct pending_work;
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+ struct tasklet_struct tx_clean_tasklet;
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};
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/* struct mtk_mac - the structure that holds the info about the MACs of the
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--
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1.7.10.4
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File diff suppressed because it is too large
Load Diff
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From b7a101f53b7cb0e05658e04accf9fd12512b5735 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 31 Mar 2016 06:46:51 +0200
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Subject: [PATCH 75/78] clk: mediatek: enable critical clocks
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/clk/mediatek/clk-mt2701.c | 22 ++++++++++++++++++++--
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1 file changed, 20 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
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index 812b347..1634288 100644
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--- a/drivers/clk/mediatek/clk-mt2701.c
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+++ b/drivers/clk/mediatek/clk-mt2701.c
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@@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[] __initconst = {
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GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
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};
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+static struct clk_onecell_data *mt7623_top_clk_data __initdata;
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+static struct clk_onecell_data *mt7623_pll_clk_data __initdata;
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+
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+static void __init mtk_clk_enable_critical(void)
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+{
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+ if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
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+ return;
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+
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+ clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
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+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
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+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
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+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
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+}
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+
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static void __init mtk_topckgen_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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@@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
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return;
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}
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- clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
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+ mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
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mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
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clk_data);
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@@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(struct device_node *node)
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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+
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+ mtk_clk_enable_critical();
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}
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CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
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@@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
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struct clk_onecell_data *clk_data;
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int r;
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- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
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+ mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
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if (!clk_data)
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return;
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@@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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+
|
||||
+ mtk_clk_enable_critical();
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
|
||||
mtk_apmixedsys_init);
|
||||
--
|
||||
1.7.10.4
|
||||
|
@ -1,306 +0,0 @@ |
||||
From cc94bef897241da9b978c9799defbdbabe9ff6ec Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 31 Mar 2016 02:26:37 +0200
|
||||
Subject: [PATCH 76/78] clk: mediatek: Export CPU mux clocks for CPU frequency
|
||||
control
|
||||
|
||||
This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
|
||||
for intermediate clock source switching.
|
||||
|
||||
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
---
|
||||
drivers/clk/mediatek/Makefile | 2 +-
|
||||
drivers/clk/mediatek/clk-cpumux.c | 127 ++++++++++++++++++++++++++++++++
|
||||
drivers/clk/mediatek/clk-cpumux.h | 22 ++++++
|
||||
drivers/clk/mediatek/clk-mt2701.c | 8 ++
|
||||
drivers/clk/mediatek/clk-mt8173.c | 23 ++++++
|
||||
include/dt-bindings/clock/mt2701-clk.h | 3 +-
|
||||
include/dt-bindings/clock/mt8173-clk.h | 4 +-
|
||||
7 files changed, 186 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/clk/mediatek/clk-cpumux.c
|
||||
create mode 100644 drivers/clk/mediatek/clk-cpumux.h
|
||||
|
||||
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
|
||||
index 5b2b91b..76bfab6 100644
|
||||
--- a/drivers/clk/mediatek/Makefile
|
||||
+++ b/drivers/clk/mediatek/Makefile
|
||||
@@ -1,4 +1,4 @@
|
||||
-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
|
||||
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
|
||||
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
|
||||
diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
|
||||
new file mode 100644
|
||||
index 0000000..91b5238
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/mediatek/clk-cpumux.c
|
||||
@@ -0,0 +1,127 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015 Linaro Ltd.
|
||||
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk-provider.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/slab.h>
|
||||
+
|
||||
+#include "clk-mtk.h"
|
||||
+#include "clk-cpumux.h"
|
||||
+
|
||||
+struct mtk_clk_cpumux {
|
||||
+ struct clk_hw hw;
|
||||
+ struct regmap *regmap;
|
||||
+ u32 reg;
|
||||
+ u32 mask;
|
||||
+ u8 shift;
|
||||
+};
|
||||
+
|
||||
+static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
|
||||
+{
|
||||
+ return container_of(_hw, struct mtk_clk_cpumux, hw);
|
||||
+}
|
||||
+
|
||||
+static u8 clk_cpumux_get_parent(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
|
||||
+ int num_parents = clk_hw_get_num_parents(hw);
|
||||
+ unsigned int val;
|
||||
+
|
||||
+ regmap_read(mux->regmap, mux->reg, &val);
|
||||
+
|
||||
+ val >>= mux->shift;
|
||||
+ val &= mux->mask;
|
||||
+
|
||||
+ if (val >= num_parents)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
|
||||
+{
|
||||
+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
|
||||
+ u32 mask, val;
|
||||
+
|
||||
+ val = index << mux->shift;
|
||||
+ mask = mux->mask << mux->shift;
|
||||
+
|
||||
+ return regmap_update_bits(mux->regmap, mux->reg, mask, val);
|
||||
+}
|
||||
+
|
||||
+static const struct clk_ops clk_cpumux_ops = {
|
||||
+ .get_parent = clk_cpumux_get_parent,
|
||||
+ .set_parent = clk_cpumux_set_parent,
|
||||
+};
|
||||
+
|
||||
+static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
|
||||
+ struct regmap *regmap)
|
||||
+{
|
||||
+ struct mtk_clk_cpumux *cpumux;
|
||||
+ struct clk *clk;
|
||||
+ struct clk_init_data init;
|
||||
+
|
||||
+ cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
|
||||
+ if (!cpumux)
|
||||
+ return ERR_PTR(-ENOMEM);
|
||||
+
|
||||
+ init.name = mux->name;
|
||||
+ init.ops = &clk_cpumux_ops;
|
||||
+ init.parent_names = mux->parent_names;
|
||||
+ init.num_parents = mux->num_parents;
|
||||
+ init.flags = mux->flags;
|
||||
+
|
||||
+ cpumux->reg = mux->mux_reg;
|
||||
+ cpumux->shift = mux->mux_shift;
|
||||
+ cpumux->mask = BIT(mux->mux_width) - 1;
|
||||
+ cpumux->regmap = regmap;
|
||||
+ cpumux->hw.init = &init;
|
||||
+
|
||||
+ clk = clk_register(NULL, &cpumux->hw);
|
||||
+ if (IS_ERR(clk))
|
||||
+ kfree(cpumux);
|
||||
+
|
||||
+ return clk;
|
||||
+}
|
||||
+
|
||||
+int __init mtk_clk_register_cpumuxes(struct device_node *node,
|
||||
+ const struct mtk_composite *clks, int num,
|
||||
+ struct clk_onecell_data *clk_data)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct clk *clk;
|
||||
+ struct regmap *regmap;
|
||||
+
|
||||
+ regmap = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(regmap)) {
|
||||
+ pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
|
||||
+ PTR_ERR(regmap));
|
||||
+ return PTR_ERR(regmap);
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < num; i++) {
|
||||
+ const struct mtk_composite *mux = &clks[i];
|
||||
+
|
||||
+ clk = mtk_clk_register_cpumux(mux, regmap);
|
||||
+ if (IS_ERR(clk)) {
|
||||
+ pr_err("Failed to register clk %s: %ld\n",
|
||||
+ mux->name, PTR_ERR(clk));
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ clk_data->clks[mux->id] = clk;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
|
||||
new file mode 100644
|
||||
index 0000000..52c769f
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/mediatek/clk-cpumux.h
|
||||
@@ -0,0 +1,22 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015 Linaro Ltd.
|
||||
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#ifndef __DRV_CLK_CPUMUX_H
|
||||
+#define __DRV_CLK_CPUMUX_H
|
||||
+
|
||||
+int mtk_clk_register_cpumuxes(struct device_node *node,
|
||||
+ const struct mtk_composite *clks, int num,
|
||||
+ struct clk_onecell_data *clk_data);
|
||||
+
|
||||
+#endif /* __DRV_CLK_CPUMUX_H */
|
||||
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
|
||||
index 1634288..5c37fcb 100644
|
||||
--- a/drivers/clk/mediatek/clk-mt2701.c
|
||||
+++ b/drivers/clk/mediatek/clk-mt2701.c
|
||||
@@ -18,6 +18,7 @@
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
+#include "clk-cpumux.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2701-clk.h>
|
||||
|
||||
@@ -465,6 +466,10 @@ static const char * const cpu_parents[] __initconst = {
|
||||
"mmpll"
|
||||
};
|
||||
|
||||
+static const struct mtk_composite cpu_muxes[] __initconst = {
|
||||
+ MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
|
||||
+};
|
||||
+
|
||||
static const struct mtk_composite top_muxes[] __initconst = {
|
||||
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
|
||||
0x0040, 0, 3, INVALID_MUX_GATE_BIT),
|
||||
@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
||||
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
|
||||
clk_data);
|
||||
|
||||
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
||||
+ clk_data);
|
||||
+
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
|
||||
index 227e356..dfb109f 100644
|
||||
--- a/drivers/clk/mediatek/clk-mt8173.c
|
||||
+++ b/drivers/clk/mediatek/clk-mt8173.c
|
||||
@@ -18,6 +18,7 @@
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
+#include "clk-cpumux.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
|
||||
@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
|
||||
"apll2_div5"
|
||||
};
|
||||
|
||||
+static const char * const ca53_parents[] __initconst = {
|
||||
+ "clk26m",
|
||||
+ "armca7pll",
|
||||
+ "mainpll",
|
||||
+ "univpll"
|
||||
+};
|
||||
+
|
||||
+static const char * const ca57_parents[] __initconst = {
|
||||
+ "clk26m",
|
||||
+ "armca15pll",
|
||||
+ "mainpll",
|
||||
+ "univpll"
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_composite cpu_muxes[] __initdata = {
|
||||
+ MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
|
||||
+ MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
|
||||
+};
|
||||
+
|
||||
static const struct mtk_composite top_muxes[] __initconst = {
|
||||
/* CLK_CFG_0 */
|
||||
MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
|
||||
@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
||||
clk_data);
|
||||
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
|
||||
|
||||
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
||||
+ clk_data);
|
||||
+
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
|
||||
index 50972d1..a6c63b8 100644
|
||||
--- a/include/dt-bindings/clock/mt2701-clk.h
|
||||
+++ b/include/dt-bindings/clock/mt2701-clk.h
|
||||
@@ -217,7 +217,8 @@
|
||||
#define CLK_INFRA_PMICWRAP 17
|
||||
#define CLK_INFRA_DDCCI 18
|
||||
#define CLK_INFRA_CLK_13M 19
|
||||
-#define CLK_INFRA_NR 20
|
||||
+#define CLK_INFRA_CPUSEL 20
|
||||
+#define CLK_INFRA_NR 21
|
||||
|
||||
/* PERICFG */
|
||||
|
||||
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
|
||||
index 7956ba1..c82ed7c 100644
|
||||
--- a/include/dt-bindings/clock/mt8173-clk.h
|
||||
+++ b/include/dt-bindings/clock/mt8173-clk.h
|
||||
@@ -192,7 +192,9 @@
|
||||
#define CLK_INFRA_PMICSPI 10
|
||||
#define CLK_INFRA_PMICWRAP 11
|
||||
#define CLK_INFRA_CLK_13M 12
|
||||
-#define CLK_INFRA_NR_CLK 13
|
||||
+#define CLK_INFRA_CA53SEL 13
|
||||
+#define CLK_INFRA_CA57SEL 14
|
||||
+#define CLK_INFRA_NR_CLK 15
|
||||
|
||||
/* PERI_SYS */
|
||||
|
||||
--
|
||||
1.7.10.4
|
||||
|
@ -1,727 +0,0 @@ |
||||
From d1421147c328a7d06d9a6b8330c73e45139b1e48 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 30 Mar 2016 23:48:53 +0200
|
||||
Subject: [PATCH 77/78] cpufreq: mediatek: add driver
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/arm/boot/dts/mt7623-evb.dts | 160 ++++++++++++----
|
||||
arch/arm/boot/dts/mt7623.dtsi | 50 ++++-
|
||||
drivers/cpufreq/Kconfig.arm | 9 +
|
||||
drivers/cpufreq/Makefile | 1 +
|
||||
drivers/cpufreq/mt7623-cpufreq.c | 389 ++++++++++++++++++++++++++++++++++++++
|
||||
5 files changed, 570 insertions(+), 39 deletions(-)
|
||||
create mode 100644 drivers/cpufreq/mt7623-cpufreq.c
|
||||
|
||||
diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
|
||||
index bc2b3f1..4a433f0 100644
|
||||
--- a/arch/arm/boot/dts/mt7623-evb.dts
|
||||
+++ b/arch/arm/boot/dts/mt7623-evb.dts
|
||||
@@ -39,6 +39,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&cpu0 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ proc-supply = <&mt6323_vproc_reg>;
|
||||
+};
|
||||
+
|
||||
&pwrap {
|
||||
pmic: mt6323 {
|
||||
compatible = "mediatek,mt6323";
|
||||
@@ -267,38 +283,36 @@
|
||||
};
|
||||
};
|
||||
|
||||
-&uart2 {
|
||||
- status = "okay";
|
||||
-};
|
||||
+&pio {
|
||||
+ nand_pins_default: nanddefault {
|
||||
+ pins_dat {
|
||||
+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
|
||||
+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
|
||||
+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
|
||||
+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
|
||||
+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
|
||||
+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
|
||||
+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
|
||||
+ <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
|
||||
+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
|
||||
+ input-enable;
|
||||
+ drive-strength = <MTK_DRIVE_8mA>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
|
||||
-&mmc0 {
|
||||
- status = "okay";
|
||||
- pinctrl-names = "default", "state_uhs";
|
||||
- pinctrl-0 = <&mmc0_pins_default>;
|
||||
- pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
- bus-width = <8>;
|
||||
- max-frequency = <50000000>;
|
||||
- cap-mmc-highspeed;
|
||||
- vmmc-supply = <&mt6323_vemc3v3_reg>;
|
||||
- vqmmc-supply = <&mt6323_vio18_reg>;
|
||||
- non-removable;
|
||||
-};
|
||||
+ pins_we {
|
||||
+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
|
||||
+ drive-strength = <MTK_DRIVE_8mA>;
|
||||
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
+ };
|
||||
|
||||
-&mmc1 {
|
||||
- status = "okay";
|
||||
- pinctrl-names = "default", "state_uhs";
|
||||
- pinctrl-0 = <&mmc1_pins_default>;
|
||||
- pinctrl-1 = <&mmc1_pins_uhs>;
|
||||
- bus-width = <4>;
|
||||
- max-frequency = <50000000>;
|
||||
- cap-sd-highspeed;
|
||||
- sd-uhs-sdr25;
|
||||
-// cd-gpios = <&pio 132 0>;
|
||||
- vmmc-supply = <&mt6323_vmch_reg>;
|
||||
- vqmmc-supply = <&mt6323_vmc_reg>;
|
||||
-};
|
||||
+ pins_ale {
|
||||
+ pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
|
||||
+ drive-strength = <MTK_DRIVE_8mA>;
|
||||
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
+ };
|
||||
+ };
|
||||
|
||||
-&pio {
|
||||
mmc0_pins_default: mmc0default {
|
||||
pins_cmd_dat {
|
||||
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
|
||||
@@ -370,11 +384,6 @@
|
||||
bias-pull-down;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
};
|
||||
-
|
||||
-// pins_insert {
|
||||
-// pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
|
||||
-// bias-pull-up;
|
||||
-// };
|
||||
};
|
||||
|
||||
mmc1_pins_uhs: mmc1 {
|
||||
@@ -422,6 +431,36 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mmc0 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default", "state_uhs";
|
||||
+ pinctrl-0 = <&mmc0_pins_default>;
|
||||
+ pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <50000000>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ vmmc-supply = <&mt6323_vemc3v3_reg>;
|
||||
+ vqmmc-supply = <&mt6323_vio18_reg>;
|
||||
+ non-removable;
|
||||
+};
|
||||
+
|
||||
+&mmc1 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default", "state_uhs";
|
||||
+ pinctrl-0 = <&mmc1_pins_default>;
|
||||
+ pinctrl-1 = <&mmc1_pins_uhs>;
|
||||
+ bus-width = <4>;
|
||||
+ max-frequency = <50000000>;
|
||||
+ cap-sd-highspeed;
|
||||
+ sd-uhs-sdr25;
|
||||
+ vmmc-supply = <&mt6323_vmch_reg>;
|
||||
+ vqmmc-supply = <&mt6323_vmc_reg>;
|
||||
+};
|
||||
+
|
||||
&usb1 {
|
||||
vusb33-supply = <&mt6323_vusb_reg>;
|
||||
vbus-supply = <&usb_p1_vbus>;
|
||||
@@ -456,3 +495,56 @@
|
||||
mediatek,reset-pin = <&pio 15 0>;
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&nand {
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&nand_pins_default>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "preloader";
|
||||
+ reg = <0x0 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@1 {
|
||||
+ label = "u-boot";
|
||||
+ reg = <0x40000 0x80000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@2 {
|
||||
+ label = "u-boot-env";
|
||||
+ reg = <0xc0000 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@3 {
|
||||
+ label = "factory";
|
||||
+ reg = <0x100000 0x40000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@4 {
|
||||
+ label = "kernel";
|
||||
+ reg = <0x140000 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@4 {
|
||||
+ label = "kernel2";
|
||||
+ reg = <0x2140000 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@5 {
|
||||
+ label = "rootfs";
|
||||
+ reg = <0x4140000 0x1000000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@6 {
|
||||
+ label = "usrdata";
|
||||
+ reg = <0x5140000 0x9f80000>;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
|
||||
index f405ec7..76d603a 100644
|
||||
--- a/arch/arm/boot/dts/mt7623.dtsi
|
||||
+++ b/arch/arm/boot/dts/mt7623.dtsi
|
||||
@@ -31,25 +31,65 @@
|
||||
#size-cells = <0>;
|
||||
enable-method = "mediatek,mt6589-smp";
|
||||
|
||||
- cpu@0 {
|
||||
+ cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
- cpu@1 {
|
||||
+ cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
- cpu@2 {
|
||||
+ cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
- cpu@3 {
|
||||
+ cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
+ clock-names = "cpu", "intermediate";
|
||||
+ operating-points = <
|
||||
+ 598000 1150000
|
||||
+ 747500 1150000
|
||||
+ 1040000 1150000
|
||||
+ 1196000 1200000
|
||||
+ 1300000 1300000
|
||||
+ >;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -300,7 +340,7 @@
|
||||
clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
|
||||
<&pericfg CLK_PERI_NFI_PAD>;
|
||||
clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
|
||||
- nand-on-flash-bbt;
|
||||
+ // nand-on-flash-bbt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
|
||||
index b1f8a73..baf945e 100644
|
||||
--- a/drivers/cpufreq/Kconfig.arm
|
||||
+++ b/drivers/cpufreq/Kconfig.arm
|
||||
@@ -81,6 +81,15 @@ config ARM_KIRKWOOD_CPUFREQ
|
||||
This adds the CPUFreq driver for Marvell Kirkwood
|
||||
SoCs.
|
||||
|
||||
+config ARM_MT7623_CPUFREQ
|
||||
+ bool "Mediatek MT7623 CPUFreq support"
|
||||
+ depends on ARCH_MEDIATEK && REGULATOR
|
||||
+ depends on ARM || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
|
||||
+ depends on !CPU_THERMAL || THERMAL=y
|
||||
+ select PM_OPP
|
||||
+ help
|
||||
+ This adds the CPUFreq driver support for Mediatek MT7623 SoC.
|
||||
+
|
||||
config ARM_MT8173_CPUFREQ
|
||||
bool "Mediatek MT8173 CPUFreq support"
|
||||
depends on ARCH_MEDIATEK && REGULATOR
|
||||
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
|
||||
index c0af1a1..e198752 100644
|
||||
--- a/drivers/cpufreq/Makefile
|
||||
+++ b/drivers/cpufreq/Makefile
|
||||
@@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += hisi-acpu-cpufreq.o
|
||||
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
|
||||
obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o
|
||||
obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
|
||||
+obj-$(CONFIG_ARM_MT7623_CPUFREQ) += mt7623-cpufreq.o
|
||||
obj-$(CONFIG_ARM_MT8173_CPUFREQ) += mt8173-cpufreq.o
|
||||
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
|
||||
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
|
||||
diff --git a/drivers/cpufreq/mt7623-cpufreq.c b/drivers/cpufreq/mt7623-cpufreq.c
|
||||
new file mode 100644
|
||||
index 0000000..8d154ce
|
||||
--- /dev/null
|
||||
+++ b/drivers/cpufreq/mt7623-cpufreq.c
|
||||
@@ -0,0 +1,389 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015 Linaro Ltd.
|
||||
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/cpu.h>
|
||||
+#include <linux/cpu_cooling.h>
|
||||
+#include <linux/cpufreq.h>
|
||||
+#include <linux/cpumask.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/pm_opp.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/thermal.h>
|
||||
+
|
||||
+#define VOLT_TOL (10000)
|
||||
+
|
||||
+/*
|
||||
+ * When scaling the clock frequency of a CPU clock domain, the clock source
|
||||
+ * needs to be switched to another stable PLL clock temporarily until
|
||||
+ * the original PLL becomes stable at target frequency.
|
||||
+ */
|
||||
+struct mtk_cpu_dvfs_info {
|
||||
+ struct device *cpu_dev;
|
||||
+ struct regulator *proc_reg;
|
||||
+ struct clk *cpu_clk;
|
||||
+ struct clk *inter_clk;
|
||||
+ struct thermal_cooling_device *cdev;
|
||||
+ int intermediate_voltage;
|
||||
+};
|
||||
+
|
||||
+static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
|
||||
+{
|
||||
+ return regulator_set_voltage(info->proc_reg, vproc,
|
||||
+ vproc + VOLT_TOL);
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
|
||||
+ unsigned int index)
|
||||
+{
|
||||
+ struct cpufreq_frequency_table *freq_table = policy->freq_table;
|
||||
+ struct clk *cpu_clk = policy->clk;
|
||||
+ struct clk *armpll = clk_get_parent(cpu_clk);
|
||||
+ struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
||||
+ struct device *cpu_dev = info->cpu_dev;
|
||||
+ struct dev_pm_opp *opp;
|
||||
+ long freq_hz, old_freq_hz;
|
||||
+ int vproc, old_vproc, inter_vproc, target_vproc, ret;
|
||||
+
|
||||
+ inter_vproc = info->intermediate_voltage;
|
||||
+
|
||||
+ old_freq_hz = clk_get_rate(cpu_clk);
|
||||
+ old_vproc = regulator_get_voltage(info->proc_reg);
|
||||
+
|
||||
+ freq_hz = freq_table[index].frequency * 1000;
|
||||
+
|
||||
+ rcu_read_lock();
|
||||
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
|
||||
+ if (IS_ERR(opp)) {
|
||||
+ rcu_read_unlock();
|
||||
+ pr_err("cpu%d: failed to find OPP for %ld\n",
|
||||
+ policy->cpu, freq_hz);
|
||||
+ return PTR_ERR(opp);
|
||||
+ }
|
||||
+ vproc = dev_pm_opp_get_voltage(opp);
|
||||
+ rcu_read_unlock();
|
||||
+
|
||||
+ /*
|
||||
+ * If the new voltage or the intermediate voltage is higher than the
|
||||
+ * current voltage, scale up voltage first.
|
||||
+ */
|
||||
+ target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
|
||||
+ if (old_vproc < target_vproc) {
|
||||
+ ret = mtk_cpufreq_set_voltage(info, target_vproc);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to scale up voltage!\n",
|
||||
+ policy->cpu);
|
||||
+ mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Reparent the CPU clock to intermediate clock. */
|
||||
+ ret = clk_set_parent(cpu_clk, info->inter_clk);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to re-parent cpu clock!\n",
|
||||
+ policy->cpu);
|
||||
+ mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
+ WARN_ON(1);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Set the original PLL to target rate. */
|
||||
+ ret = clk_set_rate(armpll, freq_hz);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to scale cpu clock rate!\n",
|
||||
+ policy->cpu);
|
||||
+ clk_set_parent(cpu_clk, armpll);
|
||||
+ mtk_cpufreq_set_voltage(info, old_vproc);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Set parent of CPU clock back to the original PLL. */
|
||||
+ ret = clk_set_parent(cpu_clk, armpll);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to re-parent cpu clock!\n",
|
||||
+ policy->cpu);
|
||||
+ mtk_cpufreq_set_voltage(info, inter_vproc);
|
||||
+ WARN_ON(1);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * If the new voltage is lower than the intermediate voltage or the
|
||||
+ * original voltage, scale down to the new voltage.
|
||||
+ */
|
||||
+ if (vproc < inter_vproc || vproc < old_vproc) {
|
||||
+ ret = mtk_cpufreq_set_voltage(info, vproc);
|
||||
+ if (ret) {
|
||||
+ pr_err("cpu%d: failed to scale down voltage!\n",
|
||||
+ policy->cpu);
|
||||
+ clk_set_parent(cpu_clk, info->inter_clk);
|
||||
+ clk_set_rate(armpll, old_freq_hz);
|
||||
+ clk_set_parent(cpu_clk, armpll);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void mtk_cpufreq_ready(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
||||
+ struct device_node *np = of_node_get(info->cpu_dev->of_node);
|
||||
+
|
||||
+ if (WARN_ON(!np))
|
||||
+ return;
|
||||
+
|
||||
+ if (of_find_property(np, "#cooling-cells", NULL)) {
|
||||
+ info->cdev = of_cpufreq_cooling_register(np,
|
||||
+ policy->related_cpus);
|
||||
+
|
||||
+ if (IS_ERR(info->cdev)) {
|
||||
+ dev_err(info->cpu_dev,
|
||||
+ "running cpufreq without cooling device: %ld\n",
|
||||
+ PTR_ERR(info->cdev));
|
||||
+
|
||||
+ info->cdev = NULL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ of_node_put(np);
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
|
||||
+{
|
||||
+ struct device *cpu_dev;
|
||||
+ struct regulator *proc_reg = ERR_PTR(-ENODEV);
|
||||
+ struct clk *cpu_clk = ERR_PTR(-ENODEV);
|
||||
+ struct clk *inter_clk = ERR_PTR(-ENODEV);
|
||||
+ struct dev_pm_opp *opp;
|
||||
+ unsigned long rate;
|
||||
+ int ret;
|
||||
+
|
||||
+ cpu_dev = get_cpu_device(cpu);
|
||||
+ if (!cpu_dev) {
|
||||
+ pr_err("failed to get cpu%d device\n", cpu);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ cpu_clk = clk_get(cpu_dev, "cpu");
|
||||
+ if (IS_ERR(cpu_clk)) {
|
||||
+ if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
|
||||
+ pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
|
||||
+ else
|
||||
+ pr_err("failed to get cpu clk for cpu%d\n", cpu);
|
||||
+
|
||||
+ ret = PTR_ERR(cpu_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ inter_clk = clk_get(cpu_dev, "intermediate");
|
||||
+ if (IS_ERR(inter_clk)) {
|
||||
+ if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
|
||||
+ pr_warn("intermediate clk for cpu%d not ready, retry.\n",
|
||||
+ cpu);
|
||||
+ else
|
||||
+ pr_err("failed to get intermediate clk for cpu%d\n",
|
||||
+ cpu);
|
||||
+
|
||||
+ ret = PTR_ERR(inter_clk);
|
||||
+ goto out_free_resources;
|
||||
+ }
|
||||
+
|
||||
+ proc_reg = regulator_get_exclusive(cpu_dev, "proc");
|
||||
+ if (IS_ERR(proc_reg)) {
|
||||
+ if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
|
||||
+ pr_warn("proc regulator for cpu%d not ready, retry.\n",
|
||||
+ cpu);
|
||||
+ else
|
||||
+ pr_err("failed to get proc regulator for cpu%d\n",
|
||||
+ cpu);
|
||||
+
|
||||
+ ret = PTR_ERR(proc_reg);
|
||||
+ goto out_free_resources;
|
||||
+ }
|
||||
+
|
||||
+ ret = dev_pm_opp_of_add_table(cpu_dev);
|
||||
+ if (ret) {
|
||||
+ pr_warn("no OPP table for cpu%d\n", cpu);
|
||||
+ goto out_free_resources;
|
||||
+ }
|
||||
+
|
||||
+ /* Search a safe voltage for intermediate frequency. */
|
||||
+ rate = clk_get_rate(inter_clk);
|
||||
+ rcu_read_lock();
|
||||
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
|
||||
+ if (IS_ERR(opp)) {
|
||||
+ rcu_read_unlock();
|
||||
+ pr_err("failed to get intermediate opp for cpu%d\n", cpu);
|
||||
+ ret = PTR_ERR(opp);
|
||||
+ goto out_free_opp_table;
|
||||
+ }
|
||||
+ info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
|
||||
+ rcu_read_unlock();
|
||||
+
|
||||
+ info->cpu_dev = cpu_dev;
|
||||
+ info->proc_reg = proc_reg;
|
||||
+ info->cpu_clk = cpu_clk;
|
||||
+ info->inter_clk = inter_clk;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+out_free_opp_table:
|
||||
+ dev_pm_opp_of_remove_table(cpu_dev);
|
||||
+
|
||||
+out_free_resources:
|
||||
+ if (!IS_ERR(proc_reg))
|
||||
+ regulator_put(proc_reg);
|
||||
+ if (!IS_ERR(cpu_clk))
|
||||
+ clk_put(cpu_clk);
|
||||
+ if (!IS_ERR(inter_clk))
|
||||
+ clk_put(inter_clk);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
|
||||
+{
|
||||
+ if (!IS_ERR(info->proc_reg))
|
||||
+ regulator_put(info->proc_reg);
|
||||
+ if (!IS_ERR(info->cpu_clk))
|
||||
+ clk_put(info->cpu_clk);
|
||||
+ if (!IS_ERR(info->inter_clk))
|
||||
+ clk_put(info->inter_clk);
|
||||
+
|
||||
+ dev_pm_opp_of_remove_table(info->cpu_dev);
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpufreq_init(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ struct mtk_cpu_dvfs_info *info;
|
||||
+ struct cpufreq_frequency_table *freq_table;
|
||||
+ int ret;
|
||||
+
|
||||
+ info = kzalloc(sizeof(*info), GFP_KERNEL);
|
||||
+ if (!info)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ ret = mtk_cpu_dvfs_info_init(info, policy->cpu);
|
||||
+ if (ret) {
|
||||
+ pr_err("%s failed to initialize dvfs info for cpu%d\n",
|
||||
+ __func__, policy->cpu);
|
||||
+ goto out_free_dvfs_info;
|
||||
+ }
|
||||
+
|
||||
+ ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
|
||||
+ if (ret) {
|
||||
+ pr_err("failed to init cpufreq table for cpu%d: %d\n",
|
||||
+ policy->cpu, ret);
|
||||
+ goto out_release_dvfs_info;
|
||||
+ }
|
||||
+
|
||||
+ ret = cpufreq_table_validate_and_show(policy, freq_table);
|
||||
+ if (ret) {
|
||||
+ pr_err("%s: invalid frequency table: %d\n", __func__, ret);
|
||||
+ goto out_free_cpufreq_table;
|
||||
+ }
|
||||
+
|
||||
+ /* CPUs in the same cluster share a clock and power domain. */
|
||||
+ cpumask_setall(policy->cpus);
|
||||
+ policy->driver_data = info;
|
||||
+ policy->clk = info->cpu_clk;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+out_free_cpufreq_table:
|
||||
+ dev_pm_opp_free_cpufreq_table(info->cpu_dev, &freq_table);
|
||||
+
|
||||
+out_release_dvfs_info:
|
||||
+ mtk_cpu_dvfs_info_release(info);
|
||||
+
|
||||
+out_free_dvfs_info:
|
||||
+ kfree(info);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
|
||||
+{
|
||||
+ struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
||||
+
|
||||
+ cpufreq_cooling_unregister(info->cdev);
|
||||
+ dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
|
||||
+ mtk_cpu_dvfs_info_release(info);
|
||||
+ kfree(info);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct cpufreq_driver mt7623_cpufreq_driver = {
|
||||
+ .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
|
||||
+ .verify = cpufreq_generic_frequency_table_verify,
|
||||
+ .target_index = mtk_cpufreq_set_target,
|
||||
+ .get = cpufreq_generic_get,
|
||||
+ .init = mtk_cpufreq_init,
|
||||
+ .exit = mtk_cpufreq_exit,
|
||||
+ .ready = mtk_cpufreq_ready,
|
||||
+ .name = "mtk-cpufreq",
|
||||
+ .attr = cpufreq_generic_attr,
|
||||
+};
|
||||
+
|
||||
+static int mt7623_cpufreq_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = cpufreq_register_driver(&mt7623_cpufreq_driver);
|
||||
+ if (ret)
|
||||
+ pr_err("failed to register mtk cpufreq driver\n");
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver mt7623_cpufreq_platdrv = {
|
||||
+ .driver = {
|
||||
+ .name = "mt7623-cpufreq",
|
||||
+ },
|
||||
+ .probe = mt7623_cpufreq_probe,
|
||||
+};
|
||||
+
|
||||
+static int mt7623_cpufreq_driver_init(void)
|
||||
+{
|
||||
+ struct platform_device *pdev;
|
||||
+ int err;
|
||||
+
|
||||
+ if (!of_machine_is_compatible("mediatek,mt7623"))
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ err = platform_driver_register(&mt7623_cpufreq_platdrv);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ /*
|
||||
+ * Since there's no place to hold device registration code and no
|
||||
+ * device tree based way to match cpufreq driver yet, both the driver
|
||||
+ * and the device registration codes are put here to handle defer
|
||||
+ * probing.
|
||||
+ */
|
||||
+ pdev = platform_device_register_simple("mt7623-cpufreq", -1, NULL, 0);
|
||||
+ if (IS_ERR(pdev)) {
|
||||
+ pr_err("failed to register mtk-cpufreq platform device\n");
|
||||
+ return PTR_ERR(pdev);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+device_initcall(mt7623_cpufreq_driver_init);
|
||||
--
|
||||
1.7.10.4
|
||||
|
@ -1,52 +0,0 @@ |
||||
From e722886f122fd3dd6240160f21937d2f21e9d910 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 31 Mar 2016 06:07:01 +0200
|
||||
Subject: [PATCH 78/78] arm: mediatek: make a7 timer work Signed-off-by: John
|
||||
Crispin <blogic@openwrt.org>
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/mt7623.dtsi | 2 ++
|
||||
arch/arm/mach-mediatek/Kconfig | 1 +
|
||||
arch/arm/mach-mediatek/mediatek.c | 1 +
|
||||
3 files changed, 4 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
|
||||
index 76d603a..cd08b6e 100644
|
||||
--- a/arch/arm/boot/dts/mt7623.dtsi
|
||||
+++ b/arch/arm/boot/dts/mt7623.dtsi
|
||||
@@ -120,6 +120,8 @@
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ clock-frequency = <13000000>;
|
||||
+ arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
topckgen: power-controller@10000000 {
|
||||
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
|
||||
index a7fef77..2c05bc31 100644
|
||||
--- a/arch/arm/mach-mediatek/Kconfig
|
||||
+++ b/arch/arm/mach-mediatek/Kconfig
|
||||
@@ -24,6 +24,7 @@ config MACH_MT6592
|
||||
config MACH_MT7623
|
||||
bool "MediaTek MT7623 SoCs support"
|
||||
default ARCH_MEDIATEK
|
||||
+ select HAVE_ARM_ARCH_TIMER
|
||||
select MIGHT_HAVE_PCI
|
||||
|
||||
config MACH_MT8127
|
||||
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
|
||||
index bcfca37..7553a8c 100644
|
||||
--- a/arch/arm/mach-mediatek/mediatek.c
|
||||
+++ b/arch/arm/mach-mediatek/mediatek.c
|
||||
@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void)
|
||||
void __iomem *gpt_base;
|
||||
|
||||
if (of_machine_is_compatible("mediatek,mt6589") ||
|
||||
+ of_machine_is_compatible("mediatek,mt7623") ||
|
||||
of_machine_is_compatible("mediatek,mt8135") ||
|
||||
of_machine_is_compatible("mediatek,mt8127")) {
|
||||
/* turn on GPT6 which ungates arch timer clocks */
|
||||
--
|
||||
1.7.10.4
|
||||
|
Loading…
Reference in new issue