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@ -292,6 +292,7 @@ pcibios_enable_device(struct pci_dev *dev, int mask) |
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* after calling pcibios_enable_device(). |
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* after calling pcibios_enable_device(). |
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*/ |
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*/ |
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if (sb_coreid(sbh) == SB_USB) { |
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if (sb_coreid(sbh) == SB_USB) { |
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printk(KERN_INFO "SB USB 1.1 init\n"); |
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sb_core_disable(sbh, sb_coreflags(sbh, 0, 0)); |
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sb_core_disable(sbh, sb_coreflags(sbh, 0, 0)); |
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sb_core_reset(sbh, 1 << 29, 0); |
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sb_core_reset(sbh, 1 << 29, 0); |
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} |
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} |
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@ -306,13 +307,22 @@ pcibios_enable_device(struct pci_dev *dev, int mask) |
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* phy components out of reset. |
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* phy components out of reset. |
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*/ |
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*/ |
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else if (sb_coreid(sbh) == SB_USB20H) { |
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else if (sb_coreid(sbh) == SB_USB20H) { |
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uint corerev = sb_corerev(sbh); |
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printk(KERN_INFO "SB USB20H init\n"); |
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printk(KERN_INFO "SB COREREV: %d\n", corerev); |
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if (!sb_iscoreup(sbh)) { |
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if (!sb_iscoreup(sbh)) { |
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printk(KERN_INFO "SB USB20H resetting\n"); |
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sb_core_reset(sbh, 0, 0); |
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sb_core_reset(sbh, 0, 0); |
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writel(0x7FF, (ulong)regs + 0x200); |
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writel(0x7FF, (ulong)regs + 0x200); |
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udelay(1); |
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udelay(1); |
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} |
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} |
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/* PRxxxx: War for 5354 failures. */ |
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/* PRxxxx: War for 5354 failures. */ |
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if (sb_corerev(sbh) == 1) { |
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if (corerev == 1 || corerev == 2) { |
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uint32 tmp; |
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uint32 tmp; |
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/* Change Flush control reg */ |
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/* Change Flush control reg */ |
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@ -320,14 +330,14 @@ pcibios_enable_device(struct pci_dev *dev, int mask) |
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tmp &= ~8; |
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tmp &= ~8; |
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writel(tmp, (uintptr)regs + 0x400); |
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writel(tmp, (uintptr)regs + 0x400); |
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tmp = readl((uintptr)regs + 0x400); |
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tmp = readl((uintptr)regs + 0x400); |
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printk("USB20H fcr: 0x%x\n", tmp); |
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printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp); |
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/* Change Shim control reg */ |
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/* Change Shim control reg */ |
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tmp = readl((uintptr)regs + 0x304); |
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tmp = readl((uintptr)regs + 0x304); |
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tmp &= ~0x100; |
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tmp &= ~0x100; |
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writel(tmp, (uintptr)regs + 0x304); |
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writel(tmp, (uintptr)regs + 0x304); |
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tmp = readl((uintptr)regs + 0x304); |
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tmp = readl((uintptr)regs + 0x304); |
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printk("USB20H shim cr: 0x%x\n", tmp); |
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printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp); |
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} |
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} |
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} else |
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} else |
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