SVN-Revision: 27558master
Imre Kaloz
14 years ago
parent
b3b0f0e49a
commit
8788b97e65
@ -0,0 +1,69 @@ |
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1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
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since the CNS3xxx SOCs have ARM11 MPcore CPU.
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2. Enable mpcore_watchdog option as module to default configuration at
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arch/arm/configs/cns3420vb_defconfig.
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Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
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---
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arch/arm/Kconfig | 1 +
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arch/arm/configs/cns3420vb_defconfig | 2 ++
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arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++
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3 files changed, 25 insertions(+), 0 deletions(-)
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -327,6 +327,7 @@ config ARCH_CNS3XXX
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select ARM_GIC
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select MIGHT_HAVE_PCI
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select PCI_DOMAINS if PCI
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+ select HAVE_ARM_TWD
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help
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Support for Cavium Networks CNS3XXX platform.
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--- a/arch/arm/configs/cns3420vb_defconfig
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+++ b/arch/arm/configs/cns3420vb_defconfig
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@@ -53,6 +53,8 @@ CONFIG_LEGACY_PTY_COUNT=16
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_VGA_CONSOLE is not set
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+CONFIG_WATCHDOG=y
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+CONFIG_MPCORE_WATCHDOG=m
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# CONFIG_HID_SUPPORT is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_MMC=y
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -159,10 +159,32 @@ static struct platform_device cns3xxx_us
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},
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};
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+/* Watchdog */
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+static struct resource cns3xxx_watchdog_resources[] = {
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+ [0] = {
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+ .start = CNS3XXX_TC11MP_TWD_BASE,
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+ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = IRQ_LOCALWDOG,
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+ .end = IRQ_LOCALWDOG,
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+ .flags = IORESOURCE_IRQ,
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+ }
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+};
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+
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+static struct platform_device cns3xxx_watchdog_device = {
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+ .name = "mpcore_wdt",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources),
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+ .resource = cns3xxx_watchdog_resources,
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+};
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+
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/*
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* Initialization
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*/
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static struct platform_device *cns3420_pdevs[] __initdata = {
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+ &cns3xxx_watchdog_device,
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&cns3420_nor_pdev,
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&cns3xxx_usb_ehci_device,
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&cns3xxx_usb_ohci_device,
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@ -0,0 +1,108 @@ |
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CNS3xxx SOCs have L310-compatible cache controller, so let's use it.
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With this patch benchmarking with 'gzip' shows that performance is
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doubled, and I'm still able to boot full-fledged userland over NFS
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(using PCIe NIC), so the support should be pretty robust.
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Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
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---
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arch/arm/mach-cns3xxx/cns3420vb.c | 2 +
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arch/arm/mach-cns3xxx/core.c | 43 +++++++++++++++++++++++++++++++++++++
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arch/arm/mach-cns3xxx/core.h | 6 +++++
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arch/arm/mm/Kconfig | 2 +-
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4 files changed, 52 insertions(+), 1 deletions(-)
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -192,6 +192,8 @@ static struct platform_device *cns3420_p
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static void __init cns3420_init(void)
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{
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+ cns3xxx_l2x0_init();
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+
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platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
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cns3xxx_ahci_init();
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -16,6 +16,7 @@
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/gic.h>
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+#include <asm/hardware/cache-l2x0.h>
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#include <mach/cns3xxx.h>
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#include "core.h"
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@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(vo
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struct sys_timer cns3xxx_timer = {
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.init = cns3xxx_timer_init,
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};
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+
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+#ifdef CONFIG_CACHE_L2X0
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+
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+void __init cns3xxx_l2x0_init(void)
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+{
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+ void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
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+ u32 val;
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+
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+ if (WARN_ON(!base))
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+ return;
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+
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+ /*
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+ * Tag RAM Control register
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+ *
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+ * bit[10:8] - 1 cycle of write accesses latency
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+ * bit[6:4] - 1 cycle of read accesses latency
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+ * bit[3:0] - 1 cycle of setup latency
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+ *
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+ * 1 cycle of latency for setup, read and write accesses
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+ */
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+ val = readl(base + L2X0_TAG_LATENCY_CTRL);
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+ val &= 0xfffff888;
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+ writel(val, base + L2X0_TAG_LATENCY_CTRL);
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+
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+ /*
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+ * Data RAM Control register
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+ *
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+ * bit[10:8] - 1 cycles of write accesses latency
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+ * bit[6:4] - 1 cycles of read accesses latency
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+ * bit[3:0] - 1 cycle of setup latency
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+ *
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+ * 1 cycle of latency for setup, read and write accesses
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+ */
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+ val = readl(base + L2X0_DATA_LATENCY_CTRL);
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+ val &= 0xfffff888;
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+ writel(val, base + L2X0_DATA_LATENCY_CTRL);
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+
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+ /* 32 KiB, 8-way, parity disable */
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+ l2x0_init(base, 0x00540000, 0xfe000fff);
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+}
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+
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+#endif /* CONFIG_CACHE_L2X0 */
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -13,6 +13,12 @@
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extern struct sys_timer cns3xxx_timer;
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+#ifdef CONFIG_CACHE_L2X0
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+void __init cns3xxx_l2x0_init(void);
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+#else
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+static inline void cns3xxx_l2x0_init(void) {}
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+#endif /* CONFIG_CACHE_L2X0 */
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+
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void __init cns3xxx_map_io(void);
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void __init cns3xxx_init_irq(void);
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void cns3xxx_power_off(void);
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -821,7 +821,7 @@ config CACHE_L2X0
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depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
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REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
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ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
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- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
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+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
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default y
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select OUTER_CACHE
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select OUTER_CACHE_SYNC
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@ -1,77 +0,0 @@ |
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--- a/drivers/watchdog/Kconfig
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+++ b/drivers/watchdog/Kconfig
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@@ -188,7 +188,7 @@ config SA1100_WATCHDOG
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config MPCORE_WATCHDOG
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tristate "MPcore watchdog"
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- depends on HAVE_ARM_TWD
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+ depends on ARCH_CNS3XXX
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help
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Watchdog timer embedded into the MPcore system.
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--- a/drivers/watchdog/mpcore_wdt.c
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+++ b/drivers/watchdog/mpcore_wdt.c
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@@ -32,11 +32,14 @@
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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+#include <linux/jiffies.h>
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+#include <linux/delay.h>
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#include <asm/smp_twd.h>
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struct mpcore_wdt {
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unsigned long timer_alive;
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+ unsigned long timer_rate;
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struct device *dev;
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void __iomem *base;
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int irq;
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@@ -98,14 +101,12 @@ static void mpcore_wdt_keepalive(struct
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unsigned long count;
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spin_lock(&wdt_lock);
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- /* Assume prescale is set to 256 */
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- count = __raw_readl(wdt->base + TWD_WDOG_COUNTER);
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- count = (0xFFFFFFFFU - count) * (HZ / 5);
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- count = (count / 256) * mpcore_margin;
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+ count = (wdt->timer_rate / 256) * mpcore_margin;
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/* Reload the counter */
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writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
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wdt->perturb = wdt->perturb ? 0 : 1;
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+
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spin_unlock(&wdt_lock);
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}
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@@ -329,6 +330,8 @@ static int __devinit mpcore_wdt_probe(st
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struct mpcore_wdt *wdt;
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struct resource *res;
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int ret;
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+ unsigned long count;
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+ u64 waitjiffies;
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/* We only accept one device, and it must have an id of -1 */
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if (dev->id != -1)
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@@ -375,6 +378,22 @@ static int __devinit mpcore_wdt_probe(st
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goto err_irq;
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}
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+ waitjiffies = get_jiffies_64() + 1;
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+ while (get_jiffies_64() < waitjiffies)
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+ udelay(10);
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+
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+ waitjiffies += 5;
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+
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+ __raw_writel(0x00000001, wdt->base + TWD_WDOG_CONTROL);
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+ __raw_writel(0xFFFFFFFFU, wdt->base + TWD_WDOG_LOAD);
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+
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+ while (get_jiffies_64() < waitjiffies)
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+ udelay(10);
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+
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+ count = __raw_readl(wdt->base + TWD_WDOG_COUNTER);
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+
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+ wdt->timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
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+
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mpcore_wdt_stop(wdt);
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platform_set_drvdata(dev, wdt);
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mpcore_wdt_dev = dev;
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@ -1,61 +0,0 @@ |
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -15,6 +15,7 @@
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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+#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_twd.h>
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#include <mach/cns3xxx.h>
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@@ -71,15 +72,29 @@ static struct map_desc cns3xxx_io_desc[]
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.pfn = __phys_to_pfn(CNS3XXX_SSP_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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+ }, {
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+ .virtual = CNS3XXX_L2C_BASE_VIRT,
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+ .pfn = __phys_to_pfn(CNS3XXX_L2C_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE,
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},
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};
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void __init cns3xxx_map_io(void)
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{
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+ iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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+#ifdef CONFIG_CACHE_L2X0
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+ void __iomem *l2x0_base = (void __iomem *) CNS3XXX_L2C_BASE_VIRT;
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+
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+ /* set RAM latencies to 1 cycle for this core tile. */
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+ writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
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+ writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
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+
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+ l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
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+#endif
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
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#endif
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- iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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}
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/* used by entry-macro.S */
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -821,7 +821,7 @@ config CACHE_L2X0
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depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
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REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
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ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
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- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
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+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
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default y
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select OUTER_CACHE
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select OUTER_CACHE_SYNC
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@@ -866,7 +866,7 @@ config ARM_L1_CACHE_SHIFT
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config ARM_DMA_MEM_BUFFERABLE
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bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
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depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
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- MACH_REALVIEW_PB11MP)
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+ MACH_REALVIEW_PB11MP || ARCH_CNS3XXX)
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default y if CPU_V6 || CPU_V6K || CPU_V7
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help
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Historically, the kernel has used strongly ordered mappings to
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