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@ -1583,7 +1583,7 @@ |
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+
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--- /dev/null
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+++ b/arch/mips/ar231x/ar5312.c
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@@ -0,0 +1,602 @@
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@@ -0,0 +1,596 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1623,8 +1623,7 @@ |
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+#include "devices.h"
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+#include "ar5312.h"
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+
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+static void
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+ar5312_misc_irq_dispatch(void)
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+static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
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+{
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+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) &
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+ ar231x_read_reg(AR531X_IMR);
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@ -1656,7 +1655,7 @@ |
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+ else if (pending & CAUSEF_IP5)
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+ do_IRQ(AR5312_IRQ_WLAN1_INTRS);
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+ else if (pending & CAUSEF_IP6)
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+ ar5312_misc_irq_dispatch();
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+ do_IRQ(AR5312_IRQ_MISC_INTRS);
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+ else if (pending & CAUSEF_IP7)
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+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
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+}
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@ -1714,11 +1713,6 @@ |
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+};
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+
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+
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+static struct irqaction cascade = {
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+ .handler = no_action,
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+ .name = "cascade",
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+};
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+
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+void __init ar5312_irq_init(void)
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+{
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+ int i;
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@ -1733,7 +1727,7 @@ |
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+ handle_level_irq);
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+ }
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+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
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+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
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+ irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
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+}
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+
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+static u32
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@ -2188,7 +2182,7 @@ |
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+
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--- /dev/null
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+++ b/arch/mips/ar231x/ar2315.c
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@@ -0,0 +1,621 @@
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@@ -0,0 +1,615 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -2230,7 +2224,7 @@ |
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+
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+static u32 gpiointmask, gpiointval;
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+
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+static inline void ar2315_gpio_irq(void)
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+static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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+{
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+ u32 pend;
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+ int bit = -1;
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@ -2256,8 +2250,7 @@ |
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+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
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+}
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+
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+static void
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+ar2315_misc_irq_dispatch(void)
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+static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
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+{
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+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
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+ ar231x_read_reg(AR2315_IMR);
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@ -2269,7 +2262,7 @@ |
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+ else if (misc_intr & AR2315_ISR_AHB)
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+ do_IRQ(AR2315_MISC_IRQ_AHB);
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+ else if (misc_intr & AR2315_ISR_GPIO)
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+ ar2315_gpio_irq();
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+ do_IRQ(AR2315_MISC_IRQ_GPIO);
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+ else if (misc_intr & AR2315_ISR_UART0)
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+ do_IRQ(AR2315_MISC_IRQ_UART0);
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+ else if (misc_intr & AR2315_ISR_WD) {
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@ -2297,7 +2290,7 @@ |
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+ else if (pending & CAUSEF_IP4)
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+ do_IRQ(AR2315_IRQ_ENET0_INTRS);
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+ else if (pending & CAUSEF_IP2)
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+ ar2315_misc_irq_dispatch();
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+ do_IRQ(AR2315_IRQ_MISC_INTRS);
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+ else if (pending & CAUSEF_IP7)
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+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
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+}
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@ -2382,11 +2375,6 @@ |
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+ .name = "ar2315_ahb_proc_interrupt",
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+};
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+
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+static struct irqaction cascade = {
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+ .handler = no_action,
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+ .name = "cascade",
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+};
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+
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+void
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+ar2315_irq_init(void)
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+{
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@ -2407,9 +2395,9 @@ |
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+ irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
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+ handle_level_irq);
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+ }
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+ setup_irq(AR2315_MISC_IRQ_GPIO, &cascade);
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+ irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
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+ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
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+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
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+ irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
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+}
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+
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+static u32
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