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@ -31,33 +31,6 @@ |
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/** onboard uart **/ |
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/** onboard uart **/ |
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#define ADM8668_UARTCLK_FREQ 62500000 |
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#define ADM8668_UARTCLK_FREQ 62500000 |
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/* registers */ |
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#define UART_DR_REG 0x00 |
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#define UART_RSR_REG 0x04 |
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#define UART_CR_REG 0x14 |
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#define UART_FR_REG 0x18 |
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#define UART_IIR_REG 0x1C |
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/* rsr reg */ |
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#define UART_FRAMING_ERR 0x01 |
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#define UART_PARITY_ERR 0x02 |
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#define UART_BREAK_ERR 0x04 |
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#define UART_OVERRUN_ERR 0x08 |
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#define UART_RX_STATUS_MASK 0x0F |
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/* cr reg */ |
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#define UART_RX_INT_EN 0x10 |
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#define UART_TX_INT_EN 0x20 |
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#define UART_RX_TIMEOUT_INT_EN 0x40 |
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/* fr reg */ |
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#define UART_RX_FIFO_EMPTY 0x10 |
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#define UART_TX_FIFO_FULL 0x20 |
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/* iir reg */ |
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#define UART_RX_INT 0x02 |
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#define UART_TX_INT 0x04 |
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#define UART_RX_TIMEOUT_INT 0x08 |
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/* interrupt controller */ |
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/* interrupt controller */ |
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#define IRQ_STATUS_REG 0x00 /* Read */ |
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#define IRQ_STATUS_REG 0x00 /* Read */ |
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