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@ -118,6 +118,18 @@ ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val) |
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mutex_unlock(&bus->mdio_lock); |
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mutex_unlock(&bus->mdio_lock); |
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} |
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} |
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static void |
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ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr, |
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u16 dbg_addr, u16 dbg_data) |
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{ |
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struct mii_bus *bus = priv->phy->bus; |
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mutex_lock(&bus->mdio_lock); |
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bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); |
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bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data); |
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mutex_unlock(&bus->mdio_lock); |
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} |
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static u32 |
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static u32 |
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ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val) |
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ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val) |
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{ |
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{ |
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@ -719,14 +731,11 @@ ar8316_hw_init(struct ar8216_priv *priv) |
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if ((i == 4) && priv->port4_phy && |
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if ((i == 4) && priv->port4_phy && |
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priv->phy->interface == PHY_INTERFACE_MODE_RGMII) { |
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priv->phy->interface == PHY_INTERFACE_MODE_RGMII) { |
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/* work around for phy4 rgmii mode */ |
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/* work around for phy4 rgmii mode */ |
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mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12); |
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ar8216_phy_dbg_write(priv, i, 0x12, 0x480c); |
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mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c); |
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/* rx delay */ |
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/* rx delay */ |
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mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0); |
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ar8216_phy_dbg_write(priv, i, 0x0, 0x824e); |
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mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e); |
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/* tx delay */ |
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/* tx delay */ |
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mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5); |
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ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47); |
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mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47); |
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msleep(1000); |
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msleep(1000); |
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} |
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} |
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