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@ -609,6 +609,7 @@ void ar71xx_ddr_flush(u32 reg); |
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#define AR933X_RESET_REG_RESET_MODULE 0x1c |
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#define AR933X_RESET_REG_RESET_MODULE 0x1c |
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#define AR933X_RESET_REG_BOOTSTRAP 0xac |
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#define AR933X_RESET_REG_BOOTSTRAP 0xac |
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#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) |
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) |
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) |
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#define AR934X_RESET_REG_RESET_MODULE 0x1c |
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#define AR934X_RESET_REG_RESET_MODULE 0x1c |
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@ -672,6 +673,7 @@ void ar71xx_ddr_flush(u32 reg); |
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#define AR724X_RESET_USB_PHY BIT(4) |
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#define AR724X_RESET_USB_PHY BIT(4) |
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#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) |
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#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) |
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#define AR933X_RESET_WMAC BIT(11) |
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#define AR933X_RESET_GE1_MDIO BIT(23) |
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#define AR933X_RESET_GE1_MDIO BIT(23) |
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#define AR933X_RESET_GE0_MDIO BIT(22) |
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#define AR933X_RESET_GE0_MDIO BIT(22) |
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#define AR933X_RESET_GE1_MAC BIT(13) |
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#define AR933X_RESET_GE1_MAC BIT(13) |
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