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@ -3,8 +3,6 @@ |
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#include <rt305x_regs.h> |
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#include <rt305x_regs.h> |
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#include <rt305x_esw_platform.h> |
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#include <rt305x_esw_platform.h> |
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#define GPIO_PRUPOSE 0x60 |
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#define GPIO_MDIO_BIT (1<<7) |
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#define RT305X_ESW_PHY_WRITE (1 << 13) |
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#define RT305X_ESW_PHY_WRITE (1 << 13) |
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#define RT305X_ESW_PHY_TOUT (5 * HZ) |
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#define RT305X_ESW_PHY_TOUT (5 * HZ) |
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#define RT305X_ESW_PHY_CONTROL_0 0xC0 |
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#define RT305X_ESW_PHY_CONTROL_0 0xC0 |
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@ -27,17 +25,6 @@ ramips_esw_rr(struct rt305x_esw *esw, unsigned reg) |
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return __raw_readl(esw->base + reg); |
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return __raw_readl(esw->base + reg); |
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} |
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} |
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static void |
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ramips_enable_mdio(int s) |
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{ |
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u32 gpio = rt305x_sysc_rr(GPIO_PRUPOSE); |
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if(s) |
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gpio &= ~GPIO_MDIO_BIT; |
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else |
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gpio |= GPIO_MDIO_BIT; |
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rt305x_sysc_wr(gpio, GPIO_PRUPOSE); |
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} |
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u32 |
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u32 |
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mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, |
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mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, |
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u32 write_data) |
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u32 write_data) |
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@ -45,7 +32,6 @@ mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, |
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unsigned long volatile t_start = jiffies; |
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unsigned long volatile t_start = jiffies; |
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int ret = 0; |
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int ret = 0; |
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ramips_enable_mdio(1); |
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while(1) |
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while(1) |
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{ |
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{ |
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if(!(ramips_esw_rr(esw, RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))) |
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if(!(ramips_esw_rr(esw, RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))) |
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@ -70,7 +56,6 @@ mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, |
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} |
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} |
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} |
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} |
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out: |
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out: |
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ramips_enable_mdio(0); |
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if(ret) |
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if(ret) |
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printk(KERN_ERR "ramips_eth: MDIO timeout\n"); |
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printk(KERN_ERR "ramips_eth: MDIO timeout\n"); |
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return ret; |
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return ret; |
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@ -111,11 +96,6 @@ rt305x_esw_hw_init(struct rt305x_esw *esw) |
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mii_mgr_write(esw, 0, 14, 0x65); //longer TP_IDL tail length
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mii_mgr_write(esw, 0, 14, 0x65); //longer TP_IDL tail length
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mii_mgr_write(esw, 0, 31, 0x8000); //select local register
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mii_mgr_write(esw, 0, 31, 0x8000); //select local register
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/* Port 5 Disabled */ |
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rt305x_sysc_wr(rt305x_sysc_rr(0x60) | (1 << 9), 0x60); //set RGMII to GPIO mode (GPIO41-GPIO50)
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rt305x_sysc_wr(0xfff, 0x674); //GPIO41-GPIO50 output mode
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rt305x_sysc_wr(0x0, 0x670); //GPIO41-GPIO50 output low
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/* set default vlan */ |
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/* set default vlan */ |
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ramips_esw_wr(esw, 0x2001, 0x50); |
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ramips_esw_wr(esw, 0x2001, 0x50); |
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ramips_esw_wr(esw, 0x504f, 0x70); |
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ramips_esw_wr(esw, 0x504f, 0x70); |
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