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@ -18,11 +18,9 @@ |
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <linux/io.h> |
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#include <asm/irq.h> |
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#include <asm/irq_cpu.h> |
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#include <asm/mipsregs.h> |
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#include <asm/ar7/ar7.h> |
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@ -45,76 +43,75 @@ |
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#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */ |
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#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */ |
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#define REG(addr) (*(volatile u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) |
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#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) |
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#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4)) |
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static void ar7_unmask_irq(unsigned int irq_nr); |
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static void ar7_mask_irq(unsigned int irq_nr); |
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static void ar7_unmask_secondary_irq(unsigned int irq_nr); |
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static void ar7_mask_secondary_irq(unsigned int irq_nr); |
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static irqreturn_t ar7_cascade(int interrupt, void *dev); |
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static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev); |
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static void ar7_ack_irq(unsigned int irq_nr); |
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static void ar7_unmask_sec_irq(unsigned int irq_nr); |
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static void ar7_mask_sec_irq(unsigned int irq_nr); |
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static void ar7_ack_sec_irq(unsigned int irq_nr); |
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static void ar7_cascade(void); |
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static void ar7_irq_init(int base); |
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static int ar7_irq_base; |
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static struct irq_chip ar7_irq_type = { |
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.typename = "AR7", |
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.name = "AR7", |
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.unmask = ar7_unmask_irq, |
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.mask = ar7_mask_irq, |
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.ack = ar7_ack_irq |
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}; |
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static struct irq_chip ar7_secondary_irq_type = { |
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static struct irq_chip ar7_sec_irq_type = { |
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.name = "AR7", |
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.unmask = ar7_unmask_secondary_irq, |
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.mask = ar7_mask_secondary_irq, |
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.unmask = ar7_unmask_sec_irq, |
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.mask = ar7_mask_sec_irq, |
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.ack = ar7_ack_sec_irq, |
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}; |
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static struct irqaction ar7_cascade_action = { |
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.handler = ar7_cascade,
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.handler = no_action, |
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.name = "AR7 cascade interrupt" |
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}; |
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static struct irqaction ar7_secondary_cascade_action = { |
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.handler = ar7_secondary_cascade,
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static struct irqaction ar7_sec_cascade_action = { |
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.handler = no_action, |
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.name = "AR7 secondary cascade interrupt" |
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}; |
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static void ar7_unmask_irq(unsigned int irq) |
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{ |
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unsigned long flags; |
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local_irq_save(flags); |
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/* enable the interrupt channel bit */ |
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REG(ESR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32); |
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local_irq_restore(flags); |
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writel(1 << ((irq - ar7_irq_base) % 32), |
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REG(ESR_OFFSET(irq - ar7_irq_base))); |
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} |
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static void ar7_mask_irq(unsigned int irq) |
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{ |
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unsigned long flags; |
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local_irq_save(flags); |
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/* disable the interrupt channel bit */ |
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REG(ECR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32); |
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local_irq_restore(flags); |
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writel(1 << ((irq - ar7_irq_base) % 32), |
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REG(ECR_OFFSET(irq - ar7_irq_base))); |
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} |
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static void ar7_unmask_secondary_irq(unsigned int irq) |
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static void ar7_ack_irq(unsigned int irq) |
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{ |
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unsigned long flags; |
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local_irq_save(flags); |
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/* enable the interrupt channel bit */ |
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REG(SEC_ESR_OFFSET) = 1 << (irq - ar7_irq_base - 40); |
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local_irq_restore(flags); |
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writel(1 << ((irq - ar7_irq_base) % 32), |
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REG(CR_OFFSET(irq - ar7_irq_base))); |
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} |
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static void ar7_mask_secondary_irq(unsigned int irq) |
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static void ar7_unmask_sec_irq(unsigned int irq) |
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{ |
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unsigned long flags; |
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local_irq_save(flags); |
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/* disable the interrupt channel bit */ |
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REG(SEC_ECR_OFFSET) = 1 << (irq - ar7_irq_base - 40); |
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local_irq_restore(flags); |
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writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); |
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} |
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static void ar7_mask_sec_irq(unsigned int irq) |
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{ |
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writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); |
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} |
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static void ar7_ack_sec_irq(unsigned int irq) |
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{ |
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writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); |
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} |
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void __init arch_init_irq(void) { |
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@ -126,80 +123,67 @@ static void __init ar7_irq_init(int base) |
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{ |
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int i; |
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/*
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Disable interrupts and clear pending |
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* Disable interrupts and clear pending |
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*/ |
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REG(ECR_OFFSET(0)) = 0xffffffff; |
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REG(ECR_OFFSET(32)) = 0xff; |
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REG(SEC_ECR_OFFSET) = 0xffffffff; |
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REG(CR_OFFSET(0)) = 0xffffffff; |
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REG(CR_OFFSET(32)) = 0xff; |
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REG(SEC_CR_OFFSET) = 0xffffffff; |
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writel(0xffffffff, REG(ECR_OFFSET(0))); |
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writel(0xff, REG(ECR_OFFSET(32))); |
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writel(0xffffffff, REG(SEC_ECR_OFFSET)); |
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writel(0xffffffff, REG(CR_OFFSET(0))); |
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writel(0xff, REG(CR_OFFSET(32))); |
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writel(0xffffffff, REG(SEC_CR_OFFSET)); |
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ar7_irq_base = base; |
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for(i = 0; i < 40; i++) { |
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REG(CHNL_OFFSET(i)) = i; |
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for (i = 0; i < 40; i++) { |
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writel(i, REG(CHNL_OFFSET(i))); |
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/* Primary IRQ's */ |
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irq_desc[i + base].status = IRQ_DISABLED; |
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irq_desc[i + base].action = NULL; |
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irq_desc[i + base].depth = 1; |
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irq_desc[i + base].chip = &ar7_irq_type; |
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set_irq_chip_and_handler(base + i, &ar7_irq_type, |
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handle_level_irq); |
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/* Secondary IRQ's */ |
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if (i < 32) { |
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irq_desc[i + base + 40].status = IRQ_DISABLED; |
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irq_desc[i + base + 40].action = NULL; |
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irq_desc[i + base + 40].depth = 1; |
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irq_desc[i + base + 40].chip = &ar7_secondary_irq_type; |
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} |
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if (i < 32) |
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set_irq_chip_and_handler(base + i + 40, |
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&ar7_sec_irq_type, |
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handle_level_irq); |
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} |
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setup_irq(2, &ar7_cascade_action); |
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setup_irq(ar7_irq_base, &ar7_secondary_cascade_action); |
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setup_irq(ar7_irq_base, &ar7_sec_cascade_action); |
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set_c0_status(IE_IRQ0); |
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} |
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static irqreturn_t ar7_cascade(int interrupt, void *dev) |
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{ |
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int irq; |
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irq = (REG(PIR_OFFSET) & 0x3F); |
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REG(CR_OFFSET(irq)) = 1 << (irq % 32); |
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do_IRQ(irq + ar7_irq_base); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev) |
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static void ar7_cascade(void) |
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{ |
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int irq = 0, i; |
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unsigned long status; |
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u32 status; |
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int i, irq; |
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status = REG(SEC_SR_OFFSET); |
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if (unlikely(!status)) { |
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spurious_interrupt(); |
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return IRQ_NONE; |
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/* Primary IRQ's */ |
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irq = readl(REG(PIR_OFFSET)) & 0x3f; |
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if (irq) { |
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do_IRQ(ar7_irq_base + irq); |
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return; |
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} |
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for (i = 0; i < 32; i++) |
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if (status & (i << 1)) { |
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irq = i + 40; |
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REG(SEC_CR_OFFSET) = 1 << i; |
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break; |
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/* Secondary IRQ's are cascaded through primary '0' */ |
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writel(1, REG(CR_OFFSET(irq))); |
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status = readl(REG(SEC_SR_OFFSET)); |
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for (i = 0; i < 32; i++) { |
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if (status & 1) { |
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do_IRQ(ar7_irq_base + i + 40); |
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return; |
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} |
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status >>= 1; |
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} |
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do_IRQ(irq + ar7_irq_base); |
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return IRQ_HANDLED; |
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spurious_interrupt(); |
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} |
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asmlinkage void plat_irq_dispatch(void) |
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{ |
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unsigned int pending = read_c0_status() & read_c0_cause(); |
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; |
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if (pending & STATUSF_IP7) /* cpu timer */ |
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do_IRQ(7); |
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else if (pending & STATUSF_IP2) /* int0 hardware line */ |
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do_IRQ(2); |
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ar7_cascade(); |
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else |
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spurious_interrupt(); |
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} |
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