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@ -34,6 +34,25 @@ |
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#define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000 |
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#define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000 |
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#define RTL8366_CHIP_CTRL_VLAN (1 << 13) |
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#define RTL8366_CHIP_CTRL_VLAN (1 << 13) |
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/* Switch Global Configuration register */ |
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#define RTL8366_SGCR 0x0000 |
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#define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0) |
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#define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4) |
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#define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3) |
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#define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0) |
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#define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1) |
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#define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2) |
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#define RTL8366_SGCR_MAX_LENGTH_16000 RTL8366_SGCR_MAX_LENGTH(0x3) |
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/* Port Enable Control register */ |
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#define RTL8366_PECR 0x0001 |
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/* Switch Security Control registers */ |
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#define RTL8366_SSCR0 0x0002 |
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#define RTL8366_SSCR1 0x0003 |
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#define RTL8366_SSCR2 0x0004 |
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#define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0) |
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#define RTL8366_RESET_CTRL_REG 0x0100 |
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#define RTL8366_RESET_CTRL_REG 0x0100 |
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#define RTL8366_CHIP_CTRL_RESET_HW 1 |
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#define RTL8366_CHIP_CTRL_RESET_HW 1 |
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#define RTL8366_CHIP_CTRL_RESET_SW (1 << 1) |
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#define RTL8366_CHIP_CTRL_RESET_SW (1 << 1) |
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@ -230,6 +249,20 @@ static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = { |
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{ 1, 6, 2, "IfOutBroadcastPkts" }, |
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{ 1, 6, 2, "IfOutBroadcastPkts" }, |
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}; |
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}; |
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#define REG_WR(_smi, _reg, _val) \ |
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do { \
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err = rtl8366_smi_write_reg(_smi, _reg, _val); \
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if (err) \
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return err; \
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} while (0) |
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#define REG_RMW(_smi, _reg, _mask, _val) \ |
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do { \
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err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
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if (err) \
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return err; \
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} while (0) |
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static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi) |
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static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi) |
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{ |
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{ |
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return container_of(smi, struct rtl8366s, smi); |
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return container_of(smi, struct rtl8366s, smi); |
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@ -270,6 +303,29 @@ static int rtl8366s_reset_chip(struct rtl8366_smi *smi) |
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return 0; |
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return 0; |
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} |
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} |
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static int rtl8366s_hw_init(struct rtl8366_smi *smi) |
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{ |
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int err; |
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/* set maximum packet length to 1536 bytes */ |
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REG_RMW(smi, RTL8366_SGCR, RTL8366_SGCR_MAX_LENGTH_MASK, |
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RTL8366_SGCR_MAX_LENGTH_1536); |
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/* enable all ports */ |
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REG_WR(smi, RTL8366_PECR, 0); |
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/* disable learning for all ports */ |
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REG_WR(smi, RTL8366_SSCR0, RTL8366_PORT_ALL); |
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/* disable auto ageing for all ports */ |
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REG_WR(smi, RTL8366_SSCR1, RTL8366_PORT_ALL); |
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/* don't drop packets whose DA has not been learned */ |
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REG_RMW(smi, RTL8366_SSCR2, RTL8366_SSCR2_DROP_UNKNOWN_DA, 0); |
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return 0; |
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} |
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static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi, |
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static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi, |
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u32 phy_no, u32 page, u32 addr, u32 *data) |
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u32 phy_no, u32 page, u32 addr, u32 *data) |
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{ |
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{ |
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@ -1327,6 +1383,10 @@ static int rtl8366s_sw_reset_switch(struct switch_dev *dev) |
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if (err) |
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if (err) |
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return err; |
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return err; |
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err = rtl8366s_hw_init(smi); |
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if (err) |
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return err; |
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return rtl8366s_reset_vlan(smi); |
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return rtl8366s_reset_vlan(smi); |
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} |
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} |
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@ -1492,12 +1552,14 @@ static int rtl8366s_setup(struct rtl8366s *rtl) |
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struct rtl8366_smi *smi = &rtl->smi; |
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struct rtl8366_smi *smi = &rtl->smi; |
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int ret; |
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int ret; |
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rtl8366s_debugfs_init(rtl); |
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ret = rtl8366s_reset_chip(smi); |
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ret = rtl8366s_reset_chip(smi); |
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if (ret) |
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if (ret) |
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return ret; |
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return ret; |
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rtl8366s_debugfs_init(rtl); |
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ret = rtl8366s_hw_init(smi); |
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return 0; |
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return ret; |
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} |
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} |
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static int rtl8366s_detect(struct rtl8366_smi *smi) |
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static int rtl8366s_detect(struct rtl8366_smi *smi) |
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